Clock distribution system

1. A clock distribution system for an integrated circuit comprising a plurality of regions connected by a pipeline communications bus, each region comprising a functional block and at least one bus node for connecting the functional block to the pipeline communications bus, characterised in that a distributed clock signal is allowed to skew between regions, wherein the clock signal is synchronized within respective region, and wherein at least one region has two or more bus nodes connected to a functional block, wherein a first of said bus nodes is connected directly to the functional block, and the remaining bus nodes connected to the functional block via a delay device.

2. A clock distribution system as claimed in claim 1 , wherein the clock signal is distributed to each functional, block and bus node, and wherein a predetermined clock insertion delay is inserted in each functional block and bus node.

3. A clock distribution system as claimed in, claim 1 , wherein the delay device comprises a clock bridge provided between the respective bus node and functional block.

4. A clock distribution system as claimed in claim 3 , wherein the clock bridge forms part of the functional block.

5. A clock distribution system as claimed in claim 1 , wherein the first bus node is connected to a central portion of the functional block.

6. A clock distribution system as claimed in claim 2 , wherein the clock insertion delay of each functional block and bus node is substantially equal.

7. A clock distribution system as claimed in claim 2 , wherein the clock insertion delay of one functional block or bus node is offset by a predetermined amount from the clock insertion delay of another functional block or bus node.

8. A clock distribution system as claimed in claim 2 , wherein the clock insertion delay is chosen in accordance with the size of the largest functional block connected to the communications bus.

9. A clock distribution system as claimed in claim 1 , wherein at least one of the regions has two or more bus nodes ( 53 b , 53 c , 53 d ) connected to a functional block ( 50 b ), each of said bus nodes ( 53 b , 53 c , 53 d ) having a substantially equal clock insertion delay ( 55 b , 55 c , 55 d ), the clock insertion delay ( 55 b , 55 c , 55 d ) of the bus nodes being different to the clock insertion delay ( 57 ) of the functional block ( 50 b ), and wherein the clock signal within the region is routed to each of said bus nodes ( 53 b , 53 c , 53 d ) via, a delay buffer ( 65 ).

10. A clock distribution system as claimed in claim 9 , wherein the clock insertion delay of the functional block ( 50 b ) is substantially equal to the sum of the delay provided by the delay buffer ( 65 ) and the clock insertion delay ( 55 b , 55 c , 55 d ) provided by a respective bus node.

11. A method of distributing a clock signal to a plurality of regions on an integrated circuit, the regions being connected by a pipeline communications bus, each region comprising a functional block and at least one bus node, the method comprising the steps of:

allowing the clock to skew between regions on the integrated circuit;

synchronising the clock within respective regions on the integrated circuit;

connecting two or more bus nodes to a functional block in at least one region; and

arranging the bus nodes in said region such that a first of said bus nodes is connected directly to the functional block, and the remaining bus nodes connected to the functional block via a delay device.

12. A method as claimed in claim 11 , wherein the clock signal is distributed to each functional block and bus node, and further comprising the step of inserting a predetermined clock insertion delay in each functional block and bus node.

13. A method as claimed in claim 11 , wherein the delay device comprises a clock bridge provided between the respective bus node and functional block.

14. A method as claimed in claim 13 , wherein the clock bridge forms part of the functional block.

15. A method as claimed in claim 11 , wherein the first bus node is connected to a central position of the functional block.

16. A method as claimed in claim 12 , wherein the clock insertion delay of each functional block and bus node is substantially equal.

17. A method as claimed in claim 12 , wherein the clock insertion delay of one functional block or bus node is offset by a predetermined amount from the clock insertion delay of another functional block or bus node.

18. A method as claimed in claim 12 , wherein the clock insertion delay is chosen in accordance with the size of the largest functional block connected to the communications bus.

19. A method as claimed in claim 11 , further comprising the steps of:

connecting two or more bus nodes ( 53 b , 53 c , 53 d ) to a functional block ( 50 b ) in at least one region, each of said bus nodes ( 53 b , 53 c , 53 d ) having a substantially equal clock insertion delay ( 55 b , 55 c , 55 d ), the clock insertion delay ( 55 b , 55 c , 55 d ) of the bus nodes being different to the clock insertion delay ( 57 ) of the functional block ( 50 b ); and

routing the clock signal within said region to each of said bus nodes ( 53 b , 53 c , 53 d ) via a delay buffer ( 65 ).

20. A method as claimed in claim 19 , wherein the clock insertion delay of the functional block ( 50 b ) is substantially equal to the sum of the delay provided by the delay buffer ( 65 ) and the clock insertion delay ( 55 b , 55 c , 55 d ) provided by a respective bus node.