Patent Assignment
Reel/Frame 024964/0861
Assignment of Assignor's Interest
Recorded: 2010-09-10
Pages: 18
Assignor
CLEARSPEED TECHNOLOGY LTD
Executed: 2010-08-18
Assignee
RAMBUS INC.
4440 EL CAMINO REAL, LOS ALTOS, CALIFORNIA, 94022
Covered Properties
(51)
Load Balanced Image Generation
Patent:
6,108,460 →
Application:
08/661,028 →
Geometry Processing of Digital Video Models and Images
Patent:
6,104,842 →
Application:
08/661,031 →
Linear Expression Evaluator
Patent:
5,850,489 →
Application:
08/661,069 →
Wavelet Texturing
Patent:
5,831,625 →
Application:
08/661,092 →
Shared Access Texturing of Computer Graphic Images
Patent:
5,892,517 →
Application:
08/661,194 →
Image Generation System,Methods and Computer Program Products Using Distributed Processing
Patent:
5,808,690 →
Application:
08/661,200 →
Non-Linear Texture Map Blending
Patent:
5,949,426 →
Application:
08/787,752 →
Luminance Controlled Color Resolution Reduction
Patent:
5,796,385 →
Application:
08/790,150 →
Image Generation Systems Having Processing Element Arrays with Direct Element Communication
Patent:
5,923,338 →
Application:
08/932,903 →
Parallel Processing of Data Matrices
Patent:
6,173,372 →
Application:
09/026,368 →
Luminance Controlled Color Resolution Reduction
Patent:
5,933,131 →
Application:
09/048,195 →
Memory Devices
Patent:
6,400,626 →
Application:
09/666,166 →
Apparatus for Use in a Computer System
Patent:
7,054,969 →
Application:
09/787,353 →
Graphics System
Memory Access Consolidation for Simd Processing Elements Having Access Indicators
Method and Aparatus for Simd Processing Using Multiple Queues
Patent:
6,898,692 →
Application:
10/019,188 →
Computer Graphics
Image Scaling
Data Processing Architectures for Packet Handling Wherein Batches of Data Packets of Unpredictable Size Are Distributed Across Processing Elements Arranged in a Simd Array Operable to Process Different Respective Packet Protocols at Once While Executing a Single Common Instruction Stream
Method for controlling the order of datagrams
Application:
10/074,019 →
Publication:
US 2002/0161926
Clock Distribution System
Data Packet Handling in Computer or Communication Systems
Packet Storage System for Traffic Handling
Traffic management architecture
Application:
10/534,346 →
Publication:
US 2005/0243829
State Engine for Data Processor
Apparatus for Use in a Computer Systems
Lookup Engine
Processor Memory System
Thread Swapping Based on a Yielding Indicator for a Simid Processing Array
Application:
11/615,833 →
Publication:
US 2008/0184017
Parallel Data Processing Apparatus
Parallel Data Processing Apparatus
Parallel Data Processing Apparatus
Plural Simd Arrays Processing Threads Fetched in Parallel and Prioritized by Thread Manager Sequentially Transferring Instructions to Array Controller for Distribution
A System and Method for Receiving a Plurality of Threads and for Supplying Core Instructions to a Processing Block Having a Plurality of Processor Arrays
Application:
11/678,556 →
Publication:
US 2007/0242074
Providing Redundant Processing Elements in a Parallel Processing Apparatus
Application:
11/748,367 →
Publication:
US 2008/0008393
Thread Manager to Control an Array of Processing Elements
Parallel Data Processing Apparatus
Application:
11/750,968 →
Publication:
US 2007/0294510
Parallel Data Processing Apparatus
Application:
11/750,982 →
Publication:
US 2008/0016318
Data Processing Architectures
Data Processing Architectures for Packet Handling Using a Simd Array
Parallel Data Processing Apparatus
Parallel Data Processing Apparatus
Parallel Data Processing Apparatus
Application:
11/759,211 →
Publication:
US 2008/0007562
Parallel Data Processing Apparatus
Application:
11/765,421 →
Publication:
US 2008/0162874
A Data Processing Apparatus Comprising an Array Controller for Separating an Instruction Stream into Processing Instructions and Data Transfer Instructions
Memory Access Consolidation for Simd Processing Elements Using Transaction Identifiers
Parallel Data Processing Apparatus
Parallel Data Processing Apparatus
Application:
11/774,500 →
Publication:
US 2008/0162875
Instruction Controller to Distribute Serial and Simd Instructions to Serial and Simd Processors
Parallel Data Processing Apparatus
Application:
12/363,690 →
Publication:
US 2009/0198898
Parallel Data Processing Apparatus
Related Assignments
(3)
Other recorded transfers of the patents in this record — the chain of ownership.
Change of Name
Jun 18, 2010
From: CLEARSPEED TECHNOLOGY PLC
To: CLEARSPEED TECHNOLOGY LIMITED
Reel/Frame 024555/0672 →
Change of Address
Jun 18, 2010
From: CLEARSPEED TECHNOLOGY LIMITED
To: CLEARSPEED TECHNOLOGY LIMITED
Reel/Frame 024555/0708 →
Change of Name
Jun 24, 2010
From: CLEARSPEED TECHNOLOGY PLC
To: CLEARSPEED TECHNOLOGY LIMITED
Reel/Frame 024576/0975 →