Thread manager to control an array of processing elements
View Patent ↗A data processing apparatus includes a plurality of processing elements arranged in a single instruction multiple data array. The apparatus is operable to process multiple instructions streams in parallel with one another.
1. A controller which is configured to control an array of processing elements, each of which includes a processing unit and an internal memory unit, the controller comprising:
a retrieval unit configured to retrieve instructions items for each of a plurality instruction streams, each instruction stream having a plurality of instruction items;
a combining unit configured to combine the plurality of instruction streams into a serial instruction stream;
an instruction distributor configured to distribute the serial instruction stream to an array of processing elements, wherein the instruction distributor is configured to distribute selectively the serial instruction stream to either an array controller which controls data processing of the array of processing elements, or to a channel controller which controls transfer of data to and from the processing elements;
a plurality of instruction stream processors, one for each instruction stream, for controlling the respective instruction streams;
a semaphore controller for controlling synchronisation between instruction streams;
a status block for providing status information regarding each of the instruction streams; and
a scheduler connected to receive status information, and configured to determine which of the instruction streams is to be active.
2. A controller as claimed in claim 1 , further comprising a cache memory for storing retrieved instructions items.
3. A controller which is configured to control an array of processing elements, each of which includes a processing unit and an internal memory unit, the controller comprising:
a retrieval unit configured to retrieve instructions items for each of a plurality instruction streams, each instruction stream having a plurality of instruction items;
a combining unit configured to combine the plurality of instruction streams into a serial instruction stream;
an instruction distributor configured to distribute the serial instruction stream to an array of processing elements, wherein the instruction distributor is configured to distribute selectively the serial instruction stream to either an array controller which controls data processing of the array of processing elements, or to a channel controller which controls transfer of data to and from the processing elements;
an instruction stream processor for controlling a plurality of instruction streams;
a semaphore controller for controlling synchronisation between instruction streams;
a status block for providing status information regarding each of the instruction streams; and
a scheduler connected to receive status information, and configured to determine which of the instruction streams is to be active.
4. A controller as claimed in claim 1 , wherein each instruction stream is assigned a relative priority level.
5. A controller as claimed in claim 1 , wherein the array of processors is a single instruction multiple data (SIMD) array.
6. A thread manager configured to control an array of processing elements, each of which includes a processing unit and an internal memory unit, the thread manager comprising:
a retrieval unit configured to retrieve instructions items from external memory for each of a plurality threads, each thread being a stream of instruction items;
a combining unit configured to combine the threads into a serial command stream; and
an instruction distributor configured to distribute selectively the serial command stream to either an array controller which controls data processing of the array of processing elements, or to a channel controller which controls transfer of data between external memory and internal memory units of the processing elements;
at least one thread processor for controlling a plurality of threads;
a semaphore controller for controlling synchronisation between threads;
a status block for providing status information regarding each of the threads; and
a scheduler configured to determine which of the threads is to be active at any particular moment in time.
7. A thread manager as claimed in claim 6 , further comprising a cache memory for buffering the instruction retrievals from memory.
8. A thread manager as claimed in claim 6 wherein the at least one thread processor for controlling a plurality of threads further comprises:
a plurality of thread processors, one for each thread, for controlling the respective thread.
9. A thread manager as claimed in claim 6 , wherein the array of processors is a single instruction multiple data (SIMD) array.
10. A controller as claimed in claim 6 , wherein each instruction stream is assigned a relative priority level.
11. A controller as claimed in claim 3 , wherein each instruction stream is assigned a relative priority level.
12. A controller as claimed in claim 3 , wherein the array of processors is a single instruction multiple data (SIMD) array.
13. A controller as claimed in claim 3 , further comprising a cache memory for storing retrieved instructions items.