PARALLEL DATA PROCESSING APPARATUS
A data processing apparatus includes a plurality of processing elements arranged in a single instruction multiple data array.
1 . A data processing apparatus comprising:
an array of processing elements, wherein each processing element includes a processing unit and an internal memory unit and is operable to process data; and
a controller for controlling the execution of a plurality of separate instruction streams on the array of processing elements.
2 . A data processing apparatus as claimed in claim 1 , wherein the array of processing elements is a SIMD (single instruction multiple data) array.
3 . A data processing apparatus as claimed in claim 1 , provided on a single integrated circuit.
4 . A graphical data processing system comprising a host general data processing apparatus and a data processing apparatus as claimed in claim 1 for processing graphical data.
5 . A data processing apparatus comprising:
an array of processing elements, wherein each processing element includes a processing unit and an internal memory unit and is operable to process data; and
a thread manager for controlling the execution of a plurality of threads on the array of processing elements, each thread being an instruction stream.
6 . A data processing apparatus as claimed in claim 5 , wherein the array of processing elements is a SIMD (single instruction multiple data) array.
7 . A data processing apparatus as claimed in claim 5 , provided on a single integrated circuit.
8 . A graphical data processing system comprising a host general data processing apparatus and a data processing apparatus as claimed in claim 5 for processing graphical data.