Apparatus for use in a computer systems
View Patent ↗Apparatus for use in a computer system comprises a bus architecture, a plurality of modules connected to the bus architecture, at least one module being latency tolerant and at least one module being latency intolerant. The bus architecture comprises a primary bus ( 3 ) having latency intolerant modules connected thereto, a secondary bus ( 4 ) having latency tolerant modules connected thereto, and a primary to secondary bus interface module ( 5 ) interconnecting the primary and secondary buses.
1. Apparatus for use in a computer system comprising:
an open-ended a pipeline bus architecture, in which data traverses the bus architecture over plurality of system clock cycles; and
a plurality of modules adapted for selective connection to the bus architecture, wherein the bus architecture comprises:
a plurality of bus connection units; and
a plurality of bus portions arranged in open-ended series, each bus portion, except the last in the series, being connected to the next portion in the series by way of a bus connection unit, each of the bus connection units including multiplexer circuitry for selectively connecting a module to the bus architecture, wherein
the modules are connected to the bus architecture only by way of the bus connection units and in response to operation of the multiplexer circuitry.
2. Apparatus as claimed in claim 1 , wherein each bus connection unit includes output circuitry connected to the bus portions to which the unit is connected, the output circuitry being tailored to optimize the signal characteristics for the physical length of the bus portions concerned.
3. Apparatus as claimed in claim 1 , wherein the bus portions are all equal in physical length.
4. Apparatus as claimed in claim 1 , wherein the pipeline bus architecture comprises a primary pipelined bus and a secondary pipelined bus, the primary and secondary buses being interconnected by an interface, a first plurality of modules connected to the primary bus by means of respective said bus connection units, and a second plurality of modules connected to the secondary bus by means of respective said bus connection units.
5. Apparatus as claimed in claim 4 , wherein the first plurality of modules are latency intolerant and the second plurality of modules are latency tolerant.
6. Apparatus as claimed in claim 4 , wherein the primary bus has a length of one pipeline stage, said length being the bus length traveled by a data pulse in a single system clock cycle.
7. Apparatus as claimed in claim 1 , wherein a central arbitration unit arbitrates between the modules in order to grant access to the bus architecture.
8. Apparatus as claimed claim 7 , wherein the pipelined bus architecture comprises a primary pipelined bus and a secondary pipelined bus, the primary and secondary buses interconnected by an interface, a first plurality of modules connected to the primary bus by means of respective said bus connection units, and a second plurality of modules connected to the secondary bus by means of respective said bus connection units.
9. Apparatus as claimed in claim 1 , wherein transactions involving data in excess of a predetermined size are split into a plurality of data packets of fixed size, said packets being independently arbitrated.
10. Apparatus as claimed in claim 1 wherein said bus architecture comprises separate read, write and transaction buses.
11. Apparatus as claimed in claim 1 , wherein the bus architecture has a width sufficient to permit read and write request transactions to alternate in successive system clock cycles.
12. A computer system comprising:
an open-ended pipeline bus architecture, in which data traverses the bus architecture over a plurality of system clock cycles; and
a plurality of modules adapted for selective connection to the bus architecture, wherein the bus architecture comprises:
a plurality of bus connection units; and
a plurality of bus portions arranged in open-ended series, each bus portion, except the last in the series, being connected to the next portion in the series by way of a bus connection unit, each of the bus connection units including multiplexer circuitry for selectively connecting a module to the bus architecture, wherein
the modules are connected to the bus architecture only by way of the bus connection units and in response to operation of the multiplexer circuitry.
13. An integrated processing device comprising:
an open-ended pipeline bus architecture, in which data traverses the bus architecture over a plurality of system clock cycles; and
a plurality of modules adapted for selective connection to the bus architecture;
wherein the bus architecture comprises:
a plurality of bus connection units; and
a plurality of bus portions arranged in an open-ended series, each bus portion, except the last in the series, being connected to the next portion in the series by way of a bus connection unit,
each of the bus connection units including multiplexer circuitry for selectively connecting a module to the bus architecture,
wherein the modules are connected to the bus architecture only by way of the bus connection units and in response to operation of the multiplexer circuitry.
14. An integrated processing device as claimed in claim 13 , wherein each bus connection unit includes output circuitry connected to the bus portions to which the unit is connected, the output circuitry being tailored to optimise the signal characteristics for the physical length of the bus portions concerned.
15. An integrated processing device as claimed in claim 13 , wherein the bus portions are all equal in physical length.
16. An integrated processing device as claimed in claim 13 , wherein the pipeline bus architecture comprises a primary pipelined bus and a secondary pipelined bus, the primary and secondary buses being interconnected by an interface, a first plurality of modules connected to the primary bus by means of respective said bus connection units, and a second plurality of modules connected to the secondary bus by means of respective said bus connection units.
17. An integrated processing device as claimed in claim 16 , wherein the first plurality of modules are latency intolerant and the second plurality of modules are latency tolerant.
18. An integrated processing device as claimed in claim 16 , wherein the primary bus has a length of one pipeline stage, said length being the bus length travelled by a data pulse in a single system clock cycle.
19. An integrated processing device as claimed in claim 13 , wherein a central arbitration unit arbitrates between the modules in order to grant access to the bus architecture.
20. An integrated processing device as claimed in claim 19 , wherein the pipelined bus architecture comprises a primary pipelined bus and a secondary pipelined bus, the primary and secondary buses interconnected by an interface, a first plurality of modules connected to the primary bus by means of respective said bus connection units, and a second plurality of modules connected to the secondary bus by means of respective said bus connection units.
21. An integrated processing device as claimed in claim 13 , wherein transactions involving data in excess of a predetermined size are split into a plurality of data packets of fixed size, said packets being independently arbitrated.
22. An integrated processing device as claimed in claim 13 , wherein said bus architecture comprises separate read, write and transaction buses.
23. An integrated processing device as claimed in claim 13 , wherein the bus architecture has a width sufficient to permit read and write request transactions to alternate in successive system clock cycles.