Semiconductor storage device and its manufacturing method
View Patent ↗A plurality of impurity diffusion layers working as bit lines are formed in surface portions of a semiconductor substrate, and a plurality of buried insulating films are formed above the plural impurity diffusion layers on the semiconductor substrate. Gate electrodes of memory devices include a plurality of first polysilicon films, which are formed between the buried insulating films with a trapping film formed below and have top faces at substantially the same level as top faces of the buried insulating films, and a second polysilicon film formed over the plural buried insulating films and the plural first polysilicon films for electrically connecting the plural first polysilicon films to one another.
1. A semiconductor memory comprising a plurality of memory devices, each one of said plurality of memory devices composed of a pair of impurity diffusion layers spaced from each other and formed in surface portions of a semiconductor substrates, a trapping film formed on said semiconductor substrate and in a region between said pair of impurity diffusion layers, and a gate electrode formed on said trapping film,
wherein one of said pair of impurity diffusion layers constituting each one of said plurality of memory devices is shared by two adjacent memory devices of said plurality of memory devices; and
an insulating film is formed filling a region between said gate electrodes of said two adjacent memory devices so that said insulating film covers the top of said impurity diffusion layer shared by said two adjacent memory devices.
2. A semiconductor memory comprising:
a plurality of impurity diffusion layers formed in surface portions of a semiconductor substrate in a shape of stripes and working as bit lines;
a plurality of buried insulating films formed above said plurality of impurity diffusion layers on said semiconductor substrate and extending along a bit line direction; and
gate electrodes of memory devices formed on said semiconductor substrate and extending along a word line direction,
wherein said gate electrodes include a plurality of first conducting films, which are formed between said plurality of buried insulating films on said semiconductor substrate with a trapping film formed below said gate electrodes and have top faces thereof at substantially the same level as top faces of said plurality of buried insulating films, and a second conducting film formed over said plurality of buried insulating films and said plurality of first conducting films for electrically connecting said plurality of first conducting films to one another.
3. The semiconductor memory of claim 1 or 2 ,
wherein said trapping film is made of a multilayer film composed of a silicon oxide film, a silicon nitride film and a silicon oxide film successively deposited on said semiconductor substrate.
4. A semiconductor memory comprising:
a plurality of impurity diffusion layers formed in surface portions of a semiconductor substrate in a shape of stripes and working as bit lines;
a plurality of buried insulating films formed above said plurality of impurity diffusion layers on said semiconductor substrate and extending along a bit line direction;
a plurality of floating electrodes made of first conducting films that are formed between said plurality of buried insulating films on said semiconductor substrate with a tunnel insulating film formed below and have top faces substantially at the same level as top faces of said plurality of buried insulating films;
an inter-electrode insulating film formed over said plurality of buried insulating films and said plurality of floating electrodes and extending along a word line direction; and
gate electrodes of memory devices made of a second conducting film that is formed on said inter-electrode insulating film and extends along the word line direction.
5. The semiconductor memory of claim 2 or 4 , further comprising sidewall insulating films formed on side faces of said first conducting films.
6. The semiconductor memory of claim 5 , further comprising metal films formed between said plurality of impurity diffusion layers and said plurality of buried insulating films and between every pair of said sidewall insulating films opposing each other.
7. The semiconductor memory of claim 2 or 4 ,
wherein each of said plurality of impurity diffusion layers includes a high concentration impurity diffusion layer formed at a center and low concentration impurity diffusion layers formed on both sides of said high concentration impurity diffusion layer.
8. The semiconductor memory of claim 2 or 4 ,
wherein a silicide layer is formed in a surface portion of said second conducting film.
9. The semiconductor memory of claim 8 , further comprising sidewall insulating films formed on side faces of said plurality of buried insulating films.
10. The semiconductor memory of claim 8 , further comprising insulating films buried between said plurality of buried insulating films.
11. The semiconductor memory of claim 2 or 4 ,
wherein said second conducting film is a metal film.
12. The semiconductor memory of claim 2 or 4 ,
wherein a transistor included in a logic circuit is provided on said semiconductor substrate, and
a gate electrode of said transistor has a multilayer structure composed of one of said plurality of first conducting films and said second conducting film.
13. The semiconductor memory of claim 12 ,
wherein a silicide layer is formed in a surface portion of said second conducting film.
14. The semiconductor memory of claim 12 ,
wherein said second conducting film is a metal film.
15. The semiconductor memory of claim 2 or 4 ,
wherein a transistor included in a logic circuit is provided on said semiconductor substrate, and
a gate electrode of said transistor is made of said second conducting film alone.