IP Library Granted Patent US 7,064,005
Granted Patent B2
US 7,064,005 · App. 10/474,863 · Granted Jun 20, 2006

Semiconductor apparatus and method of manufacturing same

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Quick Facts
Patent No.
US 7,064,005
App. No.
10/474,863
Granted
Jun 20, 2006
Kind
B2
Abstract

A semiconductor apparatus that allow miniaturization of a multichip module using an interposer substrate and a method of manufacturing the same are provided. It is configured that an embedded electrode ( 4 ) penetrating through an interposer substrate ( 1 ) is provided, one end thereof is made to be connected to a connection electrode ( 2 ) on which device chips ( 10 ) are flip-chip mounted, and connecting to an unillustrated mounting substrate via a bump electrode ( 5 ), that is, because an electrode connecting the mounting substrate is made to be drawn out from the back surface of the interposer substrate ( 1 ), a multichip module can be miniaturized.

Claims (16)

1. A method of manufacturing a semiconductor apparatus constituting a multichip module wherein a plurality of device chips are flip-chip mounted on an interposer substrate, characterized by comprising:

a first step for forming an embedded electrode by filling a contact hall penetrating through a wafer with conductor, said wafer being a base material of said interposer substrate;

a second step for forming wiring including a connection electrode connected to a first end of the embedded electrode and a connection electrode on which said device chips to be flip-chip mounted on a surface of said wafer;

a third step for forming said interposer substrate by grinding and polishing a back surface of said wafer until a second end of said embedded electrode is exposed after said plurality of device chips are flip-chip mounted on said connection electrode formed in the second step; and

a fourth step for providing a bump electrode on the second end of said embedded electrode exposed in the third step.

2. A method for manufacturing a semiconductor apparatus according to claim 1 , characterized in that said interposer substrate comprises a silicon substrate.

3. A method for manufacturing a semiconductor apparatus according to claim 1 wherein after performing the third step, the second end of said embedded electrode does not protrude past the back surface of the wafer.

4. A method for manufacturing a semiconductor apparatus according to claim 1 wherein after performing the third step, the second end of said embedded electrode is substantially even with the back surface of the wafer.

5. A method of manufacturing a semiconductor apparatus constituting a multichip module wherein a plurality of device chips are flip-chip mounted on an interposer substrate, characterized by comprising:

a first step for forming an embedded electrode by filling a contact hail penetrating through a wafer with conductor, said wafer being a base material of said interposer substrate;

a second step for forming wiring including a connection electrode connected to a first end of the embedded electrode, whereby a device chip can be flip-chip mounted to the connection electrode;

a third step for forming said interposer substrate by grinding and polishing a back surface of said wafer until a second end of said embedded electrode is exposed; and

a fourth step for providing a bump electrode on the second end of said embedded electrode exposed in the third step.

6. A method for manufacturing a semiconductor apparatus according to claim 5 , characterized in that said interposer substrate comprises a silicon substrate.

7. A method for manufacturing a semiconductor apparatus according to claim 5 wherein after performing the third step, the second end of said embedded electrode does not protrude past the back surface of the wafer.

8. A method for manufacturing a semiconductor apparatus according to claim 5 wherein after performing the third step, the second end of said embedded electrode is substantially even with the back surface of the wafer.

Assignments (6)
RELEASE OF SECURITY INTEREST Recorded Jun 11, 2020
From: ROYAL BANK OF CANADA
To: TESSERA, INC.; INVENSAS BONDING TECHNOLOGIES, INC. (F/K/A ZIPTRONIX, INC.); FOTONATION CORPORATION (F/K/A DIGITALOPTICS CORPORATION AND F/K/A DIGITALOPTICS CORPORATION MEMS); INVENSAS CORPORATION; TESSERA ADVANCED TECHNOLOGIES, INC; DTS, INC.; DTS LLC; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
Reel/Frame 052920/0001 →
SECURITY INTEREST Recorded Jun 1, 2020
From: ROVI SOLUTIONS CORPORATION; ROVI TECHNOLOGIES CORPORATION; ROVI GUIDES, INC.; TIVO SOLUTIONS INC.; VEVEO, INC.; INVENSAS CORPORATION; INVENSAS BONDING TECHNOLOGIES, INC.; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: BANK OF AMERICA, N.A.
Reel/Frame 053468/0001 →
SECURITY INTEREST Recorded Dec 2, 2016
From: INVENSAS CORPORATION; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; ZIPTRONIX, INC.; DIGITALOPTICS CORPORATION; DIGITALOPTICS CORPORATION MEMS; DTS, LLC; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: ROYAL BANK OF CANADA, AS COLLATERAL AGENT
Reel/Frame 040797/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 16, 2015
From: SONY CORPORATION
To: TESSERA ADVANCED TECHNOLOGIES, INC.
Reel/Frame 035430/0231 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 8, 2003
From: TAKAOKA, YUJI
To: SONY CORPORATION
Reel/Frame 014898/0424 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 8, 2003
From: TAKAOKA, YUJI
To: SONY CORPORATION
Reel/Frame 014987/0246 →