Non-volatile semiconductor memory

1. A non-volatile semiconductor memory comprising:

at least one EPROM/EEPROM memory cell that includes

a floating gate transistor including a field effect transistor and a polysilicon layer;

a first deposited metal interconnection layer having metal interconnects and a first metal electrode;

a second deposited metal interconnection layer having a second metal electrode;

a coupling capacitor that includes the first metal electrode, the second metal electrode, and a dielectric interposed between said first and second metal electrodes, the second metal electrode forming a control electrode of the floating gate transistor;

a first via that electrically couples the first metal electrode to the polysilicon layer of the floating gate transistor; and

a second via that electrically couples the second metal electrode to one of the metal interconnects of the first deposited metal interconnection layer.

2. A non-volatile semiconductor memory as recited in claim 1 , wherein the coupling capacitor is a MIM (Mental-Insulator-Metal) capacitor.

3. A display device equipped with an arrangement for controlling the display device, which arrangement comprises:

a non-volatile semiconductor memory including at least one EPROM/EEPROM memory cell containing

a floating gate transistor having a field effect transistor and a polysilicon layer;

a first deposited metal interconnection layer having metal interconnects and a first metal electrode;

a second deposited metal interconnection layer having a second metal electrode;

a coupling capacitor that includes the first metal electrode, the second metal electrode, and a dielectric interposed between said first and second metal electrodes, the second metal electrode forming a control electrode of the floating gate transistor;

a first via that electrically couples the first metal electrode to the polysilicon layer of the floating gate transistor; and

a second via that electrically couples the second metal electrode to one of the metal interconnects of the first deposited metal interconnection layer.

4. An arrangement for controlling a display device, which arrangement comprises:

a non-volatile semiconductor memory including at least one EPROM/EEPROM memory cell containing

a floating gate transistor having a field effect transistor and a polysilicon layer;

a first deposited metal interconnection layer having metal interconnects and a first metal electrode:

a second deposited metal interconnection layer having a second metal electrode;

a coupling capacitor that includes the first metal electrode, the second metal electrode, and a dielectric interposed between said first and second metal electrodes, the second metal electrode forming a control electrode of the floating gate transistor;

a first via that electrically couples the first metal electrode to the polysilicon layer of the floating gate transistor; and

a second via that electrically couples the second metal electrode to one of the metal interconnects of the first deposited metal interconnection layer.

5. A non-volatile semiconductor memory as recited in claim 1 , wherein the first and second metal electrodes include at least one of titanium, aluminum and copper.

6. A non-volatile semiconductor memory as recited in claim 1 , wherein the at least one EPROM/EEPROM memory cell further includes

a third deposited metal interconnection layer having metal interconnects;

a third via that electrically couples one of the metal interconnects of the third deposited metal interconnection layer to a source of the floating gate transistor;

a fourth via that electrically couples one of the metal interconnects of the third deposited metal interconnection layer to a drain of the floating gate transistor; and

a fifth via that electrically couples one of the metal interconnects of the third deposited metal interconnection layer to the polysilicon layer of the floating gate transistor.

7. A non-volatile semiconductor memory as recited in claim 6 , wherein the at least one EPROM/EEPROM memory cell further includes

a fourth deposited metal interconnection layer having metal interconnects;

a sixth via that electrically couples one of the metal interconnects of the fourth deposited metal interconnection layer to one of the metal interconnects of the third deposited metal interconnection layer; and

a seventh via that electrically couples one of the metal interconnects of the fourth deposited metal interconnection layer to the metal interconnect of the third deposited metal interconnection layer that is electrically coupled to the polysilicon layer of the floating gate transistor, and

wherein the first via electrically couples the first metal electrode of the coupling capacitor to the metal interconnect of the fourth deposited metal layer that is electrically coupled to the metal interconnect of the third deposited metal interconnection layer that is electrically coupled to the polysilicon layer of the floating gate transistor.

8. A non-volatile semiconductor memory as recited in claim 1 , wherein the dielectric interposed between the first and second metal electrodes of the coupling capacitor includes at least one of SiO 2 and Si 3 N 4 .

9. A display device as recited in claim 3 , wherein the coupling capacitor is a MIM (Metal-Insulator-Metal) capacitor.

10. A display device as recited in claim 3 , wherein the first and second metal electrodes include at least one of titanium, aluminum and copper.

11. A display device as recited in claim 3 , wherein the at least one EPROM/EEPROM memory cell further includes

a third deposited metal interconnection layer having metal interconnects;

a third via that electrically couples one of the metal interconnects of the third deposited metal interconnection layer to a source of the floating gate transistor;

a fourth via that electrically couples one of the metal interconnects of the third deposited metal interconnection layer to a drain of the floating gate transistor; and

a fifth via that electrically couples one of the metal interconnects of the third deposited metal interconnection layer to the polysilicon layer of the floating gate transistor.

12. A display device as recited in claim 11 , wherein the at least one EPROM/EEPROM memory cell further includes

a fourth deposited metal interconnection layer having metal interconnects;

a sixth via that electrically couples one of the metal interconnects of the fourth deposited metal interconnection layer to one of the metal interconnects of the third deposited metal interconnection layer; and

a seventh via that electrically couples one of the metal interconnects of the fourth deposited metal interconnection layer to the metal interconnect of the third deposited metal interconnection layer that is electrically coupled to the polysilicon layer of the floating gate transistor, and

wherein the first via electrically couples the first metal electrode of the coupling capacitor to the metal interconnect of the fourth deposited metal layer that is electrically coupled to the metal interconnect of the third deposited metal interconnection layer that is electrically coupled to the polysilicon layer of the floating gate transistor.

13. A display device as recited in claim 3 , wherein the dielectric interposed between the first and second metal electrodes of the coupling capacitor includes at least one of SiO 2 and Si 3 N 4 .

14. An arrangement for controlling a display device as recited in claim 4 , wherein the coupling capacitor is a MIM (Metal-Insulator-Metal) capacitor.

15. An arrangement for controlling a display device as recited in claim 4 , wherein the first and second metal electrodes include at least one of titanium, aluminum and copper.

16. An arrangement for controlling a display device as recited in claim 4 , wherein the at least one EPROM/EEPROM memory cell further includes

a third deposited metal interconnection layer having metal interconnects;

a third via that electrically couples one of the metal interconnects of the third deposited metal interconnection layer to a source of the floating gate transistor;

a fourth via that electrically couples one of the metal interconnects of the third deposited metal interconnection layer to a drain of the floating gate transistor; and

a fifth via that electrically couples one of the metal interconnects of the third deposited metal interconnection layer to the polysilicon layer of the floating gate transistor.

17. An arrangement for controlling a display device as recited in claim 16 , wherein the at least one EPROM/EEPROM memory cell further includes

a fourth deposited metal interconnection layer having metal interconnects;

a sixth via that electrically couples one of the metal interconnects of the fourth deposited metal interconnection layer to one of the metal interconnects of the third deposited metal interconnection layer; and

a seventh via that electrically couples one of the metal interconnects of the fourth deposited metal interconnection layer to the metal interconnect of the third deposited metal interconnection layer that is electrically coupled to the polysilicon layer of the floating gate transistor, and

wherein the first via electrically couples the first metal electrode of the coupling capacitor to the metal interconnect of the fourth deposited metal layer that is electrically coupled to the metal interconnect of the third deposited metal interconnection layer that is electrically coupled to the polysilicon layer of the floating gate transistor.

18. An arrangement for controlling a display device as recited in claim 4 , wherein the dielectric interposed between the first and second metal electrodes of the coupling capacitor includes at least one of SiO 2 and Si 3 N 4 .

19. An arrangement for controlling a display device as recited in claim 4 , wherein the first via and the second via include at least one of titanium, aluminum and copper.

20. A non-volatile semiconductor memory as recited in claim 1 , wherein the first via and the second via include at least one of titanium, aluminum and copper.