High-frequency power amplifier circuit and electronic part for communication
View Patent ↗A wireless communication system has a first operation mode (GSM mode) for amplifying a phase-modulated high frequency signal with a high frequency power amplifier circuit and a second operation mode (EDGE mode) for amplifying a phase and amplitude-modulated high frequency signal with the amplifier circuit. The amplifier circuit has an input of a high frequency signal, with the amplitude and frequency being fixed in both the first and second operation modes, and operates by being controlled for the bias state of each amplifying stage in accordance with the output control signal produced by a control circuit based on the demanded output level (Vapc) and the detected output level (VSNS) so that the amplifier circuit performs signal amplification to meet the demanded output level.
1. A high frequency power amplifier circuit, comprising:
an amplifier which comprises a power amplifying FET having a first gate terminal and a second gate terminal, said power amplifying FET being adapted to have a linear operation or saturation operation depending on a bias voltage applied to the first gate terminal; and
a bias control circuit which provides the first gate terminal of said power amplifying FET with such a first bias voltage in a first operation mode that said amplifier operates in the saturation region, and such a second bias voltage in a second operation mode that said amplifier has a linear operation, and provides the second gate terminal with a third bias voltage which suppresses the gain of said power amplifying FET.
2. A high frequency power amplifier circuit according to claim 1 , wherein said amplifier comprises an FET having two gate terminals for one channel region.
3. A high frequency power amplifier circuit according to claim 1 , wherein said amplifier comprises two FETs connected in series.
4. A high frequency power amplifier circuit according to claim 1 , including an FET which is connected to said power amplifying FET in current mirror configuration, said bias control circuit conducting certain control currents to the current mirror FET thereby to produce the bias voltages to be applied to the first and second gate terminals.
5. A high frequency power amplifier circuit for amplifying a modulated high frequency signal and releasing it, said amplifier circuit including an output detection circuit which includes a transistor for detecting the output level of the last-stage amplifier, and releasing a signal which represents the output level detected by said output detection circuit;
wherein said output detection circuit comprises a field effect transistor which receives on the gate terminal thereof an input voltage of the last-stage amplifier, and a current mirror circuit which duplicates the drain current of said field effect transistor.
6. A high frequency power amplifier circuit according to claim 1 , wherein the bias voltage is made variable during the linear operation of said power amplifying FET.
7. A high frequency power amplifier circuit, comprising:
an amplifier which comprises a power amplifying FET having a first gate terminal and a second gate terminal, said power amplifying FET being adapted to have a linear operation or saturation operation depending on a bias voltage applied to the first gate terminal; and
a bias control circuit which provides the first gate terminal of said power amplifying FET with such a first bias voltage in a first operation mode that said amplifier operates in the saturation region, and such a second bias voltage in a second operation mode that said amplifier has a linear operation, and provides the second gate terminal with a third bias voltage which suppresses the gain of said power amplifying FET,
wherein said third bias voltage is higher than said first bias voltage and said second bias voltage.
8. A high frequency power amplifier circuit according to claim 7 , wherein said amplifier comprises an FET having two gate terminals for one channel region.
9. A high frequency power amplifier circuit according to claim 7 , wherein said amplifier comprises two FETs connected in series.
10. A high frequency power amplifier circuit according to claim 7 , including a current mirror FET which is connected to said power amplifying FET in current mirror configuration, said bias control circuit conducting certain control currents to the current mirror FET thereby to produce the bias voltages to be applied to the first and second gate terminals.
11. A high frequency power amplifier circuit according to claim 7 , wherein the bias voltage is made variable during the linear operation of said power amplifying FET.