Method and arrangement for bringing together data on parallel data paths
View Patent ↗A processor arrangement having a strip structure for parallel data processing is configured so that local data from the individual processing units or strips is brought together in a rapid manner. Input data, intermediate data and/or output data from various processing units are linked together in an operation which is at least partially combinatory. The data linking operation is not clock controlled. The linking of the local data from various strips in this manner reduces delays in parallel data processing in the processor arrangement. The combinatory data linking operation can provide an overall data linking outcome within an individual clock cycle.
1. A method for bringing together data from parallel data paths in a processor arrangement, wherein data in a data memory are split and stored in data groups with a plurality of elements under one and the same address, read out from the latter and fed to processing units, wherein each element of a data group is assigned a processing unit and all elements of a data group are read out of the data memory simultaneously and in parallel and distributed as input data to the processing units and in the latter are processed clock-controlled in parallel, the method comprising the step of:
directly linking output data from the processing units using at least one operation which is combinatorial and which is not clock-controlled, wherein the using at least one operation comprises using a redundant numerical representation at least one partial step of the operation so that carries in all positions of the data are formed simultaneously and used for the next partial step; and
feeding back a produced data element or data group result of the operation into at least one of the processing unit or into a register assigned to this processing unit.
2. A processor arrangement for parallel, clock-controlled data processing with a data memory designed as group memory and parallel processing units, which are connected together via a communication unit, wherein at least one data group with a plurality of elements is stored in the group memory under one address and each data element is assigned a processing unit, the processor arrangement comprising:
at least one process unit and at least one memory unit, which are located in a strip that is adjacent to at least an additional strip of like structure;
a programmed controlled combinatorial linkage arrangement comprising at least one of an addition network, a subtraction network, and a network for minimum/maximum formation, and in which network the carry in a specified linking step is ascertainable at a position of the data independent of the preceding positions, which is not clock-controlled and which directly links together data from the strips, wherein the data comprises output data from the processing units,
wherein at least one data element or data group output register of the linkage arrangement is assigned a control latch by which the register data are separable from the linkage arrangement.
3. The method of claim 1 comprising linking data of all processing units.
4. The method of claim 1 further comprising producing a data element or a data group as the result of using the at least one operation.
5. The method of claim 1 wherein using at least one operation comprises selecting one of a plurality of combinatorial operations that are not clock- controlled operations.
6. The processor arrangement of claim 2 comprising a plurality of such linkage arrangements, wherein a selection of the linkage arrangements is program-controlled.
7. The processor arrangement of claim 2 wherein an output of the linkage arrangement is connected with a register of a processing unit or a register assigned to a data group.