Semiconductor device with a protective security coating comprising multiple alternating metal layers
View Patent ↗The semiconductor device comprises a substrate ( 10 ) with a first ( 1 ) and an opposed second side ( 2 ), at which first side a plurality of transistors and interconnects is present, which are covered by a protective security covering ( 16 ), which device is further provided with bond pad regions ( 14 ). The protective security covering ( 16 ) comprises a substantially non-transparent and substantially chemically inert security coating ( 16 ), and the bond pad regions ( 14 ) are accessible from the second side of the substrate ( 10 ). The semiconductor device can be suitable made with a substrate transfer technique, in which a second substrate ( 24 ) is provided at the protective security covering ( 16 ).
1. A semiconductor device comprising a substrate with a first and an opposed second side, at which first side a plurality of transistors and interconnects is present, which are covered by a protective security covering, which device is further provided with bond pad regions, characterized in that the protective security covering comprises a substantially non-transparent and substantially chemically inert security coating, the security coating including at least one layer of inorganic material, and the bond pad regions are accessible from the second side of the substrate,
wherein the security coating comprises,
a TiO 2 layer,
a coating layer based on monoAlunuinumPhosphate (MAP) filled with particles of either TiN or TiO 2 ; and
a multi alternating layer structure formed of Al and W layers, respectively.
2. The semiconductor device as recited in claim 1 , characterized in that
the bond pad regions are present on the first side of the substrate, and
the substrate is a silicon substrate, that is patterned as required for access to the bond pad regions.
3. The semiconductor device as recited in claim 1 , characterized in that a security layer is present at the second side of the substrate, which security layer leaves exposed the bond pad regions or any metallisation for access thereto.
4. The semiconductor device as recited in claim 1 , characterized in that the bond pad regions are protected against probing with antiprobe means.
5. A carrier comprising a semiconductor device, according to claim 1 .
6. The semiconductor device as recited in claim 1 , wherein the security coating is is patterned.
7. The semiconductor device as recited in claim 6 , wherein the security coating is patterned to provide capacitive coupling from the semiconductor device to an antenna structure in a carrier.
8. The semiconductor device as recited in claim 1 , wherein the security coating is patterned to provide capacitive coupling from the semiconductor device to an antenna structure in a carrier.
9. A semiconductor device comprising a substrate with a first and an opposed second side, at which first side a plurality of transistors and interconnects is present, which are covered by a protective security covering, which device is further provided with bond pad regions, characterized in that the protective security covering comprises a substantially non-transparent and substantially chemically inert security coating, the security coating including at least one layer of inorganic material, and is formed of multiple alternate layers, which alternate layers are sensitive to different etchants and the bond pad regions are accessible from the second side of the substrate,
wherein the security coating comprises,
a TiO 2 layer,
a coating layer based on monoAluminiumPhosphate (MAP) filled with particles of either TiN or TiO 2 , and
a multi alternating layer structure formed of Al and W layers, respectively.