IP Library Granted Patent US 7,508,515
Granted Patent B2
US 7,508,515 · App. 10/513,058 · Granted Mar 24, 2009

System and method for manufacturing printed circuit boards employing non-uniformly modified images

Assignee: Orbotech Ltd
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Quick Facts
Patent No.
US 7,508,515
App. No.
10/513,058
Granted
Mar 24, 2009
Kind
B2
Abstract

A system and method for fabricating an electrical circuit in which a digital control image ( 46 ) is generated by non-uniformly modifying ( 44 ) a representation of an electrical circuit ( 40 ), such that an electrical circuit pattern ( 72 ) recorded on a substrate ( 12 ) using the digital control image ( 46 ) precisely fits an already formed electrical circuit portion ( 62 ).

Claims (39)

1. A method for fabricating an electrical circuit, comprising:

sensing an actual location of each of a plurality of alignment targets that are distributed on a plurality of electrical circuit substrates, thus detecting unintentional distortions;

providing image data of an electrical circuit pattern to be recorded on said substrates;

non-uniformly modifying said image data based on an average of the actual locations of the plurality of alignment targets, thus creating modified image data; and

recording said electrical circuit pattern on said electrical circuit substrates according to said modified image data, such that recorded features of the electrical circuit pattern are distorted in accordance with the unintentional distortions.

2. An electrical circuit fabricated according to the method of claim 1 .

3. An electrical circuit fabricating system operating according to the method of claim 1 .

4. A circuit fabrication method, comprising:

detecting unintentional distortions based on a difference between actual and planned locations of a plurality of alignment targets on a plurality of electrical circuit substrates;

modifying a planned version of a circuit pattern, based on the difference between an average of the actual locations and the planned locations of the alignment targets, so as to provide a non-uniformly modified version of the circuit pattern; and

fabricating the circuit pattern according to the modified version of the circuit pattern, such that fabricated features of the circuit pattern are distorted in accordance with the unintentional distortions.

5. The circuit fabrication method as set forth in claim 4 , wherein the alignment targets include vias.

6. The circuit fabrication method as set forth in claim 4 , wherein the modified version is produced by globally modifying the planned version in a non-uniform transform.

7. The circuit fabrication method as set forth in claim 4 , wherein the circuit pattern comprises a plurality of sectors, and the modified version is produced by modifying the planned version on a sector by sector basis.

8. The circuit fabrication method as set forth in claim 4 , wherein:

a plurality of circuit boards are fabricated according to the modified version.

9. The circuit fabrication method as set forth in claim 4 , wherein:

the modified version is generated as a control file, and a look up table is prepared based on the control file; and

the look up table is used in the fabrication of the circuit pattern to adjust exposure conditions.

10. An electrical circuit fabricated according to the method of claim 4 .

11. An electrical circuit fabricating system operating according to the method of claim 4 .

12. A circuit fabrication method, comprising:

creating a look up table based on a difference between locations of a plurality of targets on a plurality of actually-recorded versions and on a planned version of a circuit pattern, the actually-recorded versions including unintentional distortions;

determining averages of the locations of the plurality of targets on the plurality of actually-recorded versions;

using the look up table to modify conditions for scanning; and

scanning a substrate and fabricating an electrical circuit to be scanned according to the modified conditions, such that alignment targets of the electrical circuit to be scanned are scanned onto locations corresponding to the average locations of the alignment targets on the actually-recorded versions of the circuit pattern.

13. The circuit fabrication method as set forth in claim 12 , wherein the conditions for scanning in the scanning direction are modified by:

inputting a clock signal;

modifying the clock signal according to the look up table to produce a modified clock signal; and

modulating a planned version of the circuit pattern to be scanned according to the modified clock signal to produce a data signal;

wherein the scanning the substrate and fabricating the electrical circuit to be scanned comprises scanning using the data signal clocked using the modified clock signal.

14. The circuit fabrication method as set forth in claim 12 , wherein scanning a substrate and fabricating the electrical circuit to be scanned according to the modified conditions comprises moving the substrate in the cross scanning direction at a rate based on the contents of the look up table.

15. An electrical circuit fabricated according to the method of claim 12 .

16. An electrical circuit fabricating system operating according to the method of claim 12 .

17. A method for fabricating an electrical circuit, comprising:

sensing actual locations of a plurality of alignment targets that are distributed on a plurality of recorded electrical circuit substrates;

providing image data of an electrical circuit pattern to be recorded on a substrate;

non-uniformly modifying said image data based on an average of the actual locations of the plurality of alignment targets, thus creating modified image data; and

recording said electrical circuit on said substrate according to said modified image data, such that recorded features of the electrical circuit are distorted in accordance with the actual locations of the plurality of alignment targets.

Assignments (3)
RELEASE OF SECURITY INTEREST Recorded Jul 5, 2016
From: JPMORGAN CHASE BANK, N.A.
To: ORBOTECH LIMITED
Reel/Frame 039256/0711 →
PATENT SECURITY AGREEMENT Recorded Mar 7, 2016
From: ORBOTECH LTD.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 038021/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 19, 2005
From: HANINA, GOLAN; GINO, HANAN; RUECKER, STEFFEN; BEN-TOV, IDO
To: ORBOTECH LTD.
Reel/Frame 016725/0339 →
Continuity (2)
Provisional Application 6037687400 · May 2, 2002
Related Publication 20050213806A1 · Sep 29, 2005