Method of fabrication SiGe heterojunction bipolar transistor
A method of fabricating a semiconductor device includes a SiGe(C) heterojunction bipolar transistor using a non-selective epitaxial growth where an insulating layer is formed on a substrate and a layer structure including a conductive layer is provided on the insulating layer. A transistor area opening is etched through the conductive layer, and an SiGe base layer is deposited inside the transistor area opening. An insulator is formed on an upper surface so as to fill the transistor area opening, wherein prior to filling the opening, a nitride layer is formed as an inner layer of the transistor area opening.
1. A method of fabricating a semiconductor device comprising an SiGe heterojunction bipolar transistor using a non-selective epitaxial growth including the acts of forming an insulating layer on a substrate and providing a layer structure including a conductive layer on the insulating layer, etching a transistor area opening through the conductive layer, depositing a SiGe base layer inside the transistor area opening and forming an insulator on an upper surface so as to fill the transistor area opening, wherein prior to the filling step, a nitride layer is formed as an inner layer of the transistor area opening, removing an upper portion of said insulator formed on said upper surface, and etching the SiGe base layer whilst employing the nitride layer formed within the transistor area opening as a mask.
2. The method as claimed in claim 1 including the acts of forming insulating regions to replace etched upper sidewall regions of the SiGe base layer.
3. The method as claimed in claim 2 and including the act of re-oxidation of the upper sidewall region of the SiGe base layer.
4. A method of fabricating a semiconductor device comprising an SiGe heterojunction bipolar transistor using a non-selective epitaxial growth including the acts of forming an insulating layer on a substrate and providing a layer structure including a conductive layer on the insulating layer, etching a transistor area opening through the conductive layer, depositing a SiGe base layer inside the transistor area opening and forming an insulator on an upper surface so as to fill the transistor area opening, wherein prior to the filling step, a nitride layer is formed as an inner layer of the transistor area opening wherein, prior to the deposition of the SiGe base layer, a selective collector region is implanted in the substrate aligned with the transistor area opening.
5. A method of fabricating a semiconductor device comprising an SiGe heterojunction bipolar transistor using a non-selective epitaxial growth including the acts of forming an insulating layer on a substrate and providing a layer structure including a conductive layer on the insulating layer, etching a transistor area opening through the conductive layer, depositing a SiGe base layer inside the transistor area opening and forming an insulator on an upper surface so as to fill the transistor area opening, wherein prior to the filling step, a nitride layer is formed as an inner layer of the transistor area opening, wherein the multi-layer structure includes a layer of TEOS and amorphous silicon formed on the conductive layer.
6. A method of fabricating a semiconductor device comprising an SiGe heterojunction bipolar transistor using a non-selective epitaxial growth including the acts of forming an insulating layer on a substrate and providing a layer structure including a conductive layer on the insulating layer, etching a transistor area opening through the conductive layer, depositing a SiGe base layer inside the transistor area opening and forming an insulator on an upper surface so as to fill the transistor area opening, wherein prior to the filling step, a nitride layer is formed as an inner layer of the transistor area opening, wherein said SiGe base layer is formed on an inner wall of the transistor area opening and over said conductive layer, and wherein a silicon-emitter cap layer is formed on the SiGe base layer such that the nitride layer is then formed on the silicon-emitter cap layer.
7. The method as claimed in claim 6 , and including the acts of etching the nitride using the insulator formed to fill the transistor area opening as a mask.
8. The method as claimed in claim 6 , and including the step of etching the silicon-emitter cap layer and the SiGe base layer while using the oxide formed to fill the transistor area opening, and the nitride layer as a mask.
9. The method as claimed in claim 6 , and including the acts of removing the silicon emitter cap layer and the SiGe base layer from regions away from the transistor area opening.
10. The method as claimed in claim 8 , and including the acts of forming a further insulating layer over the conductive layer.