IP Library Granted Patent US 7,098,746
Granted Patent B2
US 7,098,746 · App. 10/523,891 · Granted Aug 29, 2006

Voltage controlled oscillator

Assignee: Koninklijke Phillps Electronics N.V.
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Quick Facts
Patent No.
US 7,098,746
App. No.
10/523,891
Granted
Aug 29, 2006
Kind
B2
Abstract

A voltage-controlled oscillator comprising a LC tank circuit coupled to a pair of transistors and crossed-coupled to a pair of emitter follower transistors each transistor having a collector, an emitter and a base, the voltage controlled oscillator being characterized in that a supply voltage applied to the collectors of the emitter follower transistors is substantially different from a supply voltage applied to the bases of the emitter follower transistors.

Claims (4)

1. A voltage-controlled oscillator comprising a LC tank circuit coupled to a pair of transistors and crossed-coupled to a pair of emitter follower transistors, each transistor having a collector, an emitter and a base, the voltage controlled oscillator being characterized in that a supply voltage applied to the collectors of the emitter follower transistors is substantially different from a simply voltage applied to the bases of the emitter follower transistors, and

wherein the LC tank circuit is coupled to the supply voltage via a bipolar transistor connected as a diode for obtaining a substantially different supply voltages for the bases and collectors of the emitter follower transistors.

2. A pseudo random sequence generator comprising a first sequence generator and a second sequence generator driven by a voltage controlled oscillator as claimed in claim 1 , a first output of the first sequence generator and a second output of the second sequence generator being coupled to a multiplexer driven by an output signal of the voltage controlled oscillator for selecting either a signal outputted by the first sequence generator or a signal outputted by the second sequence generator, the multiplexer generating at a third output a binary signal having a bit-rate that is substantially double a bit-rate obtained either at the first output or at the second output.

3. A pseudo random sequence generator as claimed in claim 2 , wherein each of the sequence generators comprises a closed-chain of flip-flops each having a data input, a clock input, a preset input and an output, the pseudo random sequence generator further comprising a feedback including a XOR gate having an output coupled to a first of the flip-flops data input and a pair of inputs coupled to a pair of outputs of the flip-flops.

Assignments (4)
CHANGE OF NAME Recorded Sep 22, 2017
From: PHILIPS SEMICONDUCTORS INTERNATIONAL B.V.
To: NXP B.V.
Reel/Frame 043951/0436 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 22, 2017
From: KONINKLIJKE PHILIPS ELECTRONICS N.V.
To: PHILIPS SEMICONDUCTORS INTERNATIONAL B.V.
Reel/Frame 043955/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 15, 2006
From: KONINKLIJKE PHILIPS ELECTRONICS N.V.
To: NXP B.V.
Reel/Frame 018635/0787 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 4, 2005
From: HEIJDEN, EDWIN; VEENSTRA, HUGO
To: KONINKLIJKE PHILIPS ELECTRONICS N.V.
Reel/Frame 016820/0395 →
Priority Claims (1)
EP 02078287 · Aug 8, 2002 · regional
Continuity (1)
Related Publication 20050258912A1 · Nov 24, 2005