Fail-safe method and circuit
View Patent ↗A method and a circuit for producing a fail-safe output signal in case of an open circuit condition of an input pad of a digital circuit unit, comprising a first inverter stage providing a constant switch level; a second inverter stage providing a variable switch level that depends of the signal level of the input pad and comparing the constant switch level of the first inverter stage with the variable switch level of the second stage and providing an output signal at an output terminal thereof if the variable switch level of the second stage is greater than the constant switch level; and an additional circuit clement connected in series with the second inverter for decreasing the switch level of the second inverter stage.
1. A method for producing a fail-safe output signal in case of an open circuit condition of an input pad of a digital circuit unit, the method comprising:
providing a constant switch level in a first inverter stage;
providing a variable switch level in a second inverter stage that depends on a signal level of the input pad;
comparing the constant switch level of the first inverter stage with the variable switch level of the second stage; and
providing an output signal at an output terminal thereof if the switch level of the second stage is greater than the constant switch level; and
decreasing the switch level of the second inverter stage by an additional circuit element connected in series with the second inverter,
a defined output being produced irrespective of the open circuit condition of the input pad.
2. A fail-safe circuit for producing a fail-safe output signal in case of an open circuit condition of an input pad of a digital circuit unit, the fail-safe circuit comprising:
a first inverter stage providing a constant switch level;
a second inverter stage providing a variable switch level that depends on a signal level of the input pad and comparing the constant switch level of the first inverter stage with the variable switch level of the second stage and providing an output signal at an output terminal thereof if the variable switch level of the second stage is greater than the constant switch level; and
an additional circuit element connected in series with the second inverter for decreasing the switch level of the second inverter stage;
wherein the fail-safe circuit produces a defined output irrespective of the open circuit condition of the input pad.
3. The circuit of claim 2 , wherein the first inverter stage includes at least two transistors each having a gate electrode and a drain electrode, and wherein the gate electrodes and the drain electrodes of the at least two transistors are connected to each other.
4. The circuit of claim 2 , wherein the second inverter stage includes at least two transistors each having a gate electrode and a drain electrode, and wherein the gate electrodes of the at least two transistors are connected to each other and wherein the drain electrodes of the at least two transistors are connected to each other.
5. The circuit of claim 2 , wherein gate electrodes of the second inverter stage are connected to gate electrodes of the first inverter stage.
6. The circuit of claim 2 , wherein the input pad is connected to a source electrode of the second inverter stage.
7. The circuit of claim 2 , wherein the output terminal is connected to a drain electrode of the second inverter stage.
8. The circuit of claim 2 , wherein the additional circuit element is a transistor in saturated mode.
9. The circuit of claim 2 , wherein the additional circuit element is a transistor in saturated mode, the transistor having a gate that is connected to VCC and a source that is connected to ground, the output signal being a high level signal.
10. The circuit of claim 2 , wherein the additional circuit element is a transistor in saturated mode, the transistor having a gate that is connected to ground and a source that is connected to VCC, the output signal being a low level signal.
11. A digital circuit unit comprising an input terminal, a pull-up stage, a fail-safe stage for producing a fail-safe output signal in case of an open circuit condition of the input terminal, a signal processing stage and an output terminal, wherein the fail-safe stage comprises:
a first inverter stage providing a constant switch level,
a second inverter stage providing a variable switch level that depends on a signal level of the input terminal and comparing the constant switch level of the first inverter stage with the variable switch level of the second stage and providing an output signal at the output terminal if the variable switch level of the second stage is greater than the constant switch level, and
an additional circuit element connected in series with the second inverter for decreasing the switch level of the second inverter stage;
wherein the fail-safe circuit produces a defined output irrespective of the open circuit condition of the input terminal.