Semiconductor devices and methods of manufacture thereof
View Patent ↗A semiconductor device, for example a MOSFET or IGBT, includes a region ( 30, 36, 50 ) in the drain drift region ( 14 ) juxtaposed with its channel-accommodating region ( 15 ) and spaced from the drain contact region ( 14 a ) by means of an intermediate portion of the drift region. The region comprises alternating stripes ( 31, 32 ) of the first and second conductivity types, which stripes extend alongside the channel-accommodating region ( 15 ). In a trench gated device the stripes are elongated in a direction perpendicular to the trench walls. In a planar gate device the stripes extend around the periphery of the channel-accommodating region ( 15 ) leaving the region near the gate in a direction perpendicular with respect to the gate electrotes. The dimensions and doping levels of the stripes ( 31, 32 ) are selected such that region ( 30, 36, 50 ) provides a voltage-sustaining space-charge zone when depleted. The invention enables reduction of lateral current spreading resistance in the drain drift region ( 14 ) without significantly degrading the breakdown properties of the device.
1. A semiconductor device including a semiconductor body comprising a source region and a drain region of a first conductivity type, having therebetween a channel-accommodating region, the drain region comprising a drain drift region ( 14 ) and a drain contact region, with the drain drift region between the channel-accommodating region and the drain contact region, and the drain drift region being doped to a lesser degree than the drain contact region, an insulated gate separated from the channel-accommodating region by a gate insulating layer, and a localized region in the drain drift region juxtaposed with the channel-accommodating region, the localized region comprising alternating stripes of the first conductivity type and a second, opposite conductivity type, which stripes extend laterally alongside the channel accommodating region and away from the gate, the dimensions and doping levels of the stripes being such that the localized region provides a voltage-sustaining space-charge zone when depleted.
2. A device of claim 1 , wherein the localised region adjoins the channel-accommodating region.
3. A device of claim 1 , wherein the localised region is laterally spaced from the gate insulating layer.
4. A device of claim 1 , wherein the average doping level of the localized region is substantially the same as that of an adjacent portion of the drain drift region.
5. A device of claim 1 , wherein the gate is provided in a trench, the trench extending through the channel-accommodating region into the drain drift region.
6. A device of claim 5 comprising a plurality of adjacent cells, each including a gate in a trench, wherein a deep diffusion region of the second conductivity type is provided between adjacent trenches, the deep diffusion region being doped co a greater extent that the channel accommodating region.
7. A device of claim 5 wherein the lower boundary of the localized region is above the bottom of the gate trenches.
8. A device of claim 1 , 2 or 3 wherein the channel-accommodating region is a region of an opposite, second conductivity type.
9. A method of manufacturing a semiconductor device including a semiconductor body comprising a source region and a drain region of a first conductivity type, having therebetween a channel-accommodating region, the drain region comprising a drain drift region and a drain contact region, with the drain drift region between the channel-accommodating region and the drain contact region, and the drain drift region being doped to a lesser degree that the drain contact region, and an insulated gate separated from the channel-accommodating region by a gate insulating layer, the method including the step of:
forming a localised region in the drain drift region juxtaposed with the channel-accommodating region, the localized region comprising alternating stripes of the first conductivity type and a second, opposite conductivity type, which stripes extend laterally alongside the channel-accommodating region and away from the gate.
10. A method of claim 9 wherein the localised region forming step comprises implanting a dopant of one of the first and second conductivity types, defining a striped mask over the semiconductor body, and implanting a dopant of the other of the first and second conductivity types.