Electronic memory component with protection against light attack
View Patent ↗In order to further develop an electronic memory component ( 100 or 100′ ), comprising at least one memory cell matrix ( 10 ) which is embedded in and/or let into at least one doped receiving substrate ( 20 ), in such a way that a light incidence taking the form of a so-called light attack is detected directly or sensed immediately without dead times (=contribution to chip development), it is proposed,—that the receiving substrate ( 20 ) be covered and/or surrounded at least partially and/or on at least one of its surfaces remote from the memory cell matrix ( 10 ) by at least one top/protective substrate ( 30 ) oppositely doped to the receiving substrate ( 20 ) and—that at least one of the substrates ( 20 or 30 ), for example the receiving substrate ( 20 ) and/or in particular the top/protective substrate ( 30 ), be in contact ( 12 a or 12 b ) or connection ( 32 ) with at least one circuit arrangement ( 24 or 34 respectively) for the detection of voltages or currents caused by charge carriers generated upon light incidence.
1. An electronic memory component, comprising:
a receiving substrate, wherein the receiving substrate is doped;
a memory cell matrix embedded in the receiving substrate;
a top/protective substrate to at least partially surround the receiving substrate on at least one side of the receiving substrate remote from the memory cell matrix, wherein the top/protective substrate is doped opposite to the receiving substrate; and
a circuit arrangement in contact with at least one substrate of the receiving substrate and the top/protective substrate for detection of a voltage or a current from the at least one substrate of the receiving substrate and the top/protective substrate, other than from a dedicated light sensor circuit component, in response to generation of charge carriers in the at least one substrate upon light incidence on the electronic memory component.
2. The electronic memory component of claim 1 , wherein the circuit arrangement comprises a comparator circuit.
3. The electronic memory component of claim 2 , wherein the comparator circuit is connected with the receiving substrate, via an electrical contact, to detect the voltage or the current in the receiving substrate.
4. The electronic memory component of claim 2 , wherein the comparator circuit is connected with the top/protective substrate, via an electrical contact, to detect the voltage or the current in the top/protective substrate.
5. The electronic memory component of claim 1 , wherein the electronic memory component is configured to deny access to the memory component in response to detection by the circuit arrangement of the voltage in excess of a limit voltage or the current in excess of a limit current.
6. The electronic memory component of claim 1 , wherein the electronic memory component is configured to emit an alarm to a controlling central processing unit (CPU) in response to detection by the circuit arrangement of the voltage in excess of a limit voltage or the current in excess of a limit current.
7. The electronic memory component of claim 1 , wherein the top/protective substrate comprises a well to surround the receiving substrate.
8. The electronic memory component of claim 1 , further comprising a carrier substrate, wherein the top/protective substrate is associated with the carrier substrate.
9. The electronic memory component of claim 8 , wherein the top/protective substrate is buried in the carrier substrate.
10. The electronic memory component of claim 8 , wherein:
the receiving substrate comprises a p-doped substrate;
the top/protective substrate comprises an n-doped substrate; and
the carrier substrate comprises another p-doped substrate.
11. The electronic memory component of claim 1 , further comprising:
an external source associated with the memory cell matrix, wherein the external source comprises a contact;
a bitline associated with the memory cell matrix;
a wordline associated with the memory cell matrix; and
a control gate associated with the memory cell matrix.
12. The electronic memory component of claim 1 , wherein the electronic memory component comprises an erasable programmable read only memory (EPROM), an electrical erasable programmable read only memory (EEPROM), or a Flash memory.
13. The electronic memory component of claim 1 , wherein the electronic memory component is configured to continuously detect for light incidence in the form of a light attack.
14. The electronic memory component of claim 1 , wherein the electronic memory component is on a smart card.
15. The electronic memory component of claim 3 , wherein the receiving substrate comprises an integral, large-area light sensor to generate the charge carriers in the receiving substrate, wherein the receiving substrate is configured to generate the charge carriers in response to the light incidence on any part of the receiving substrate.
16. The electronic memory component of claim 3 , wherein the receiving substrate covers a majority of a surface area of the electronic memory component, wherein the receiving substrate is configured to generate the charge carriers in response to the light incidence on any part of the receiving substrate.
17. The electronic memory component of claim 4 , wherein the top/protective substrate comprises an integral, large-area light sensor to generate the charge carriers in the top/protective substrate, wherein the top/protective substrate is configured to generate the charge carriers in response to the light incidence on any part of the top/protective substrate.
18. The electronic memory component of claim 4 , wherein the top/protective substrate covers a majority of an area of the electronic memory component, wherein the top/protective substrate is configured to generate the charge carriers in response to the light incidence on any part of the top/protective substrate.