IP Library Granted Patent US 7,157,337
Granted Patent B2
US 7,157,337 · App. 10/544,412 · Granted Jan 2, 2007

Method of manufacturing a semiconductor device and semiconductor device obtained by means of such a method

Assignee: Koninklijke Philips Electronics N.V.
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Quick Facts
Patent No.
US 7,157,337
App. No.
10/544,412
Granted
Jan 2, 2007
Kind
B2
Abstract

Consistent with an example embodiment according to the invention, a material for the intermediate layer is chosen which can be selectively etched with respect to the dielectric layer. Before the deposition of the first conductor layer, the intermediate layer is removed at the location of the first channel region, and after the deposition of the first conductor layer and the removal thereof outside the first channel region and before the deposition of the second conductor layer, the intermediate layer is removed at the location of the second channel region. Thus, field effect transistors (FETs) are obtained in a simple manner and without damage to their gate dielectric. Preferably, a further intermediate layer is deposited on the intermediate layer which can be selectively etched with respect thereto.

Claims (18)

1. A method of manufacturing a semiconductor device with a substrate and a semiconductor body the semiconductor device including a first field effect transistor with a first source, drain and channel region of a first conductivity type and a first gate electrode including a first conductor the first conductor is separated from the channel region by a dielectric layer, and the semiconductor device further including a second field effect transistor with a second source, drain and channel region of a second conductivity type, opposite to the first conductivity type, and a second gate electrode includes a second conductor that is different from the first conductor, and the second conductor is separated from the channel region by a dielectric layer, the method comprising:

wherein to form the gate electrodes a first conductor layer is applied to the semiconductor body provided with the dielectric layer,

which first conductor layer is subsequently removed outside the first channel region,

after the first conductor layer is removed, a second conductor layer is applied to the semiconductor body, and wherein, before the first conductor layer is applied, an intermediate layer is provided on the dielectric layer, the intermediate layer is provided with a further intermediate layer, the material of the further intermediate layer being selectively etchable with respect to the material of the intermediate layer,

wherein the intermediate layer is made of a material that is selectively etchable with respect to the dielectric layer,

and before the first conductor layer is provided, the intermediate layer is removed at the location of the first channel region,

and after the first conductor layer has been provided and removed outside the first channel region, and before the second conductor layer is provided,

the intermediate layer is removed at the location of the second channel region, and

wherein the intermediate layer is locally removed by etching in areas defined by a photoresist mask.

2. The method as recited in claim 1 , wherein for the material of the further intermediate layer a metal is chosen with respect to the material of the further intermediate layer, the first conductor is selectively etchable.

3. The method as recited in claim 2 , wherein aluminum is chosen as the material for the further intermediate layer.

4. The method as recited in claim 1 , wherein SiO 2 is chosen as the material for the dielectric layer, characterized in that Si is chosen as the material for the intermediate layer.

5. The method as recited in claim 1 , wherein thermal SiO 2 is chosen as the material for the dielectric layer, characterized in that sputtered SiO 2 is chosen as the material for the intermediate layer.

6. The method as recited in claim 1 , wherein Si x O y N z having a comparatively high oxygen content is chosen as the material for the dielectric layer, characterized in that Si 3 N 4 or Si is chosen as the material for the intermediate layer.

7. The method as recited in claim 1 , wherein Si x O y N z having a comparatively low oxygen content is chosen as the material for the dielectric layer, characterized in that SiO 2 is chosen as the material for the intermediate layer.

8. The method as recited in claim 1 , characterized in that the first conductivity type is chosen to be the n-type, and for the first conductor layer a material is chosen from the group composed of tantalum, tungsten, titanium or a nitride of these materials, and for the second conductor layer a metal silicide is chosen.

9. The method as recited in claim 1 , characterized in that the superfluous parts of the first conductor layer ( 33 ) as well as the superfluous parts of the second conductor layer ( 55 ) are removed by means of etching.

10. A semiconductor device obtained the method as recited in claim 1 .

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 3, 2012
From: NXP B.V.
To: IMEC
Reel/Frame 027654/0244 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 17, 2007
From: KONINKLIJKE PHILIPS ELECTRONICS N.V.
To: NXP B.V.
Reel/Frame 019719/0843 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 3, 2005
From: LANDER, ROBERT; KNOTTER, DIRK
To: KONINKLIJKE PHILIPS ELECTRONICS N.V.
Reel/Frame 017561/0031 →
Priority Claims (1)
EP 03100213 · Feb 3, 2003 · regional
Continuity (1)
Related Publication 20060138475A1 · Jun 29, 2006