Method of fabricating substrateless thin film field-effect devices and an organic thin film transistor obtainable by the method

1. A method for the manufacture of a thin-film field-effect device comprising, on a mechanical support layer, source and drain electrodes (S, D) suitable for operating as the source and collector of a flow of charge carriers within the device, and a layer of semiconductor material (SC) disposed between the electrodes (S, D) for the formation of a conduction channel the resistance of which is modulated by the application of a predetermined control voltage to a gate electrode (G) insulated from the channel region, characterized in that it comprises, in succession, the steps of:

providing a mechanical support layer in the form of a film (INS) of flexible, electrically-insulating material,

arranging the film (INS) in an extended condition so that it has substantially smooth free surfaces, the surfaces being suitable for receiving metallizations (MET) for the formation of electrodes (S, D),

forming the source and drain electrodes (S, D) in accordance with a predetermined configuration on a first surface of the insulating film,

forming the gate electrode (G) in accordance with a predetermined configuration on the part of the surface of the insulating film (INS) opposite to that carrying the source and drain electrodes (S, D), and

depositing the layer of semiconductor material (SC) between the source and drain electrodes (S, D);

wherein the flexible film (INS) constituting the mechanical support is transparent and the gate electrode (G) is formed by the successive steps of:

defining an electrode configuration substantially complementary with the configuration of the source and drain electrodes (S, D) on an intermediate coating layer (R), by a lithographic technique and by selective masking determined by the configuration of the source and drain electrodes (S, D) formed on the first surface of the film (INS), and

selective metallization in accordance with the electrode configuration thus obtained.

2. A method according to claim 1 characterized in that the definition of the configuration of the gate electrode (G) includes the steps of:

applying an intermediate coating layer of positive resist (R) to an extensive area on the opposite surface of the film (INS) to that carrying the source and drain electrodes (S, D),

exposing the resist (R) by illumination through the first surface of the film (INS) carrying the source and drain electrodes (S, D) and the transparent film (INS),

developing and selectively removing the exposed resist (R), and

depositing a metallization layer (MET) on an extensive area and subsequently selectively removing the metallization by removal of the residual resist.

3. A method according to claim 2 , characterized in that the development of the resist (R) takes place after a bath in a toluene or chlorobenzene solution.

4. A method according to claim 2 , characterized in that the source and drain electrodes (S, D) are formed from a metallization layer (MET) deposited on an extensive area of the surface of the insulating film (INS), the definition of the configuration taking place by a lithographic technique, by selective masking (M) of the metallization layer (MET) in accordance with a configuration corresponding to the geometry of the electrodes.

5. A method according to claim 4 , characterized in that the step of forming the source and drain electrodes (S, D) by lithography includes, after the deposition of the metallization layer (MET),

applying a positive resist intermediate coating layer (R) to the metallization layer (MET),

positioning a mask (M) carrying the configuration of the electrodes, exposing the resist (R) for transposition of the configuration of the electrodes onto it, and

developing the resist (R) and selectively removing the exposed areas so as to bring about transfer of the pattern of the mask (M) onto the metallization area (MET) which covers the insulating film (INS),

the metallization layer (MET) outside the regions covered by the resist (R) being exposed to a subsequent chemical etching step for its selective removal.

6. A method according to claim 1 , characterized in that the definition of the configuration of the source and drain electrodes (S, D) takes place by a lithographic technique by selective masking in accordance with a configuration corresponding to the geometry of the electrodes in negative form and includes the steps of:

applying a positive resist intermediate coating layer (R) to an extensive area of the surface of the film (INS),

exposing the resist (R) by illumination through the mask,

developing and selectively removing the exposed resist (R), and

depositing a metallization layer (MET) and subsequently selectively removing the metallization by chemical removal of the residual resist.

7. A method according to claim 5 , characterized in that the deposition of the resist layer (R) on the metallization layer (MET) of the first surface of the film (INS) and on the opposite surface are performed simultaneously.

8. A method according to claim 1 , in which the lithographic technique is an optical lithography process.

9. A method according to claim 1 , in which the lithographic technique for the formation of the source and drain electrodes is an electronic lithography process.

10. A method according to claim 1 , in which the metallization layer (MET) for the formation of the source and drain electrodes is formed by ink jet printing with conductive organic liquids or with conductive inks.

11. A method according to claim 1 , in which the metallization layer (MET) for the formation of the source and drain electrodes is formed by lithography.

12. A method according to claim 1 , in which the flexible, transparent, electrically-insulating film (INS) is a polyethylene terephthalate film.

13. A method according to claim 12 in which the thickness of the film (INS) is less than one micron.