Patent Assignment
Reel/Frame 033678/0096
Change of Address
Recorded: 2014-09-03
Pages: 41
Assignor
CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
Executed: 2014-08-20
Assignee
CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
390 MARCH ROAD, SUITE 100, OTTAWA, ON, K2K 0G7, CANADA
Covered Properties
(1439)
Delay Locked Loop Implementation In A Synchronous Dynamic Random Access Memory
Application:
14/134,996 →
Publication:
US US20140104969A1
Semiconductor Memory Asynchronous Pipeline
Process, Voltage, Temperature Independent Switched Delay Compensation Scheme
High Bandwidth Memory Interface
Application:
13/966,891 →
Publication:
US US20130329482A1
Dual Control Analog Delay Element
Application:
14/063,178 →
Method and Apparatus for Providing a Packet Buffer Random Access Memory
Application:
14/175,142 →
Publication:
US US20140153582A1
Method and Apparatus for Reducing Pool Starvation in a Shared Memory Switch
Trunking in a Matrix
Application:
14/227,412 →
Publication:
US US20140211802A1
Method and System for Packet Processing
Congestion Management in a Network
Wide Frequency Range Delay Locked Loop
Application:
14/092,788 →
Publication:
US US20140084977A1
Charge Pump for Pll/Dll
Patent:
47,715 →
Application:
14/334,347 →
Delay Locked Loop Circuit and Method
Application:
14/257,635 →
Publication:
US US20140225651A1
Voltage Down Converter for High Speed Memory
Application:
14/080,302 →
Publication:
US US20140071781A1
Method and System for Accessing a Flash Memory Device
Power Managers for an Integrated Circuit
Low Leakage and Data Retention Circuitry
Systems and Methods for Minimizing Static Leakage of an Integrated Circuit
Patent:
48,410 →
Application:
14/209,455 →
Non-Volatile Memory Bank and Page Buffer Therefor
Flash Memory System Control Scheme
Application:
12/855,171 →
Publication:
US US20100325353A1
Non-Volatile Semiconductor Memory with Page Erase
Application:
13/969,184 →
Publication:
US US20130336063A1
Flash Multi-Level Threshold Distribution Scheme
Dynamic Random Access Memory with Fully Independent Partial Array Refresh Function
Flash Memory Program Inhibit Scheme
Application:
13/652,947 →
Publication:
US US20130343123A2
Synchronous Memory Read Data Capture
Patent:
46,819 →
Application:
14/141,686 →
Apparatus and Method for Establishing Device Identifiers for Serially Interconnected Devices
Application:
13/676,606 →
Publication:
US US20130073754A1
Daisy Chain Cascading Devices with Input/Output Control
Application:
11/496,278 →
Publication:
US US20070076502A1
Daisy Chain Cascading Devices
Hybrid Solid-State Memory System Having Volatile and Non-Volatile Memory
Application:
14/197,505 →
Publication:
US US20140185379A1
Memory with Output Control
Nonvolatile memory system
Application:
11/639,375 →
Publication:
US US20070165457A1
Nonvolatile Memory System
Application:
12/578,115 →
Publication:
US US20100030951A1
Packet Data Id Generation for Serially Interconnected Devices
Application:
14/185,401 →
Publication:
US US20140173322A1
Circuit for Clamping Current in a Charge Pump
Apparatus and Method for Capturing Serial Input Data
Id Generation Apparatus and Method for Serially Interconnected Devices
Delay Locked Loop Circuit
Application:
14/316,212 →
System and Method of Page Buffer Operation for Memory Devices
System and Method of Page Buffer Operation for Memory Devices
Semiconductor Device and Method for Reducing Power Consumption in a System Having Interconnected Devices
Application:
12/018,272 →
Publication:
US US20080201588A1
Simplified Bias Circuitry for Differential Buffer Stage with Symmetric Loads
Application:
14/050,811 →
Modular Command Structure for Memory and Memory System
Application:
13/016,396 →
Publication:
US US20110131383A1
Balanced Pseudo-Random Binary Sequence Generator
Dynamic Impedance Control for Input/Output Buffers
Apparatus and Method of Page Program Operation for Memory Devices with Mirror Back-Up of Data
Dynamic Random Access Memory and Boosted Voltage Producer Therefor
Application:
13/973,574 →
Publication:
US US20130343142A1
Dynamic Random Access Memory and Boosted Voltage Producer Therefor
Daisy-chain memory configuration and usage
Application:
11/897,105 →
Publication:
US US20090063786A1
Pre-Charge Voltage Generation and Power Saving Modes
Partial Block Erase Architecture for Flash Memory
Non-Volatile Semiconductor Memory Having Multiple External Power Supplies
Data processing with time-based memory access
Ring-Of-Clusters Network Topologies
Scalable Memory System
Application:
14/172,946 →
Publication:
US US20140195715A1
Clock Mode Determination in a Memory System
Semiconductor Memory Device Suitable for Interconnection in a Ring Topology
Apparatus and Method for Using a Page Buffer of a Memory Device as a Temporary Cache
Hierarchical Common Source Line Structure in Nand Flash Memory
Application:
14/159,823 →
Publication:
US US20140133236A1
Non-Volatile Semiconductor Memory Device with Power-Saving Feature
Nand Flash Memory Having Multiple Cell Substrates
Clock Reproducing and Timing Method in a System Having a Plurality of Devices
Nand flash memory access with relaxed timing constraints
Application:
12/286,959 →
Publication:
US US20090187701A1
Non-Volatile Memory Device Having Configurable Page Size
System Having One or More Memory Devices
Application:
14/331,036 →
Publication:
US US20140325178A1
Data Storage and Stackable Chip Configurations
Mass Data Storage System with Non-Volatile Memory Modules
Bridge Device Architecture for Connecting Discrete Memory Devices to a System
System Including a Plurality of Encapsulated Semiconductor Chips
Error Detection Method and a System Including One or More Memory Devices
Termination Circuit for on-Die Termination
Application:
13/903,319 →
Publication:
US US20130249592A1
Stacked Semiconductor Devices Including a Master Device
Nand Flash Architecture with Multi-Level Row Decoding
Bridge Device Having a Virtual Page Buffer
Application:
12/607,680 →
Publication:
US US20100115172A1
Bridging Device Having a Configurable Virtual Page Size
Simultaneous Read and Write Data Transfer
Bridging Device Having a Frequency Configurable Clock Domain
Application:
13/955,809 →
Publication:
US US20130318287A1
Using Interrupted Through-Silicon-Vias in Integrated Circuits Adapted for Stacking
Package-Level Integrated Circuit Connection Without Top Metal Pads or Bonding Wire
Application:
14/193,436 →
Publication:
US US20140179059A1
System and Method Providing Interoperability Between Cellular and Other Wireless Systems
Reconfiguring Through Silicon Vias in Stacked Multi-Die Packages
Phase Change Memory Word Line Driver
Semiconductor Memory Device with Plural Memory Die and Controller Die
Dram Memory Cells Reconfigured to Provide Bulk Capacitance
Application:
13/834,009 →
Publication:
US US20140016389A1
Multi-Chip Package with Offset Die Stacking and Method of Making Same
Composite Semiconductor Memory Device with Error Correction
Memory System Having a Plurality of Serially Connected Devices
Semiconductor Memory Device Having a Three-Dimensional Structure
Application:
13/636,574 →
Publication:
US US20130016557A1
Phase Change Memory Array Blocks with Alternate Selection
Application:
13/044,701 →
Publication:
US US20110261613A1
Phase Change Memory with Double Write Drivers
Application:
13/636,585 →
Publication:
US US20130021844A1
System of Interconnected Nonvolatile Memories Having Automatic Status Packet
Status Indication in a System Having a Plurality of Memory Devices
Application:
13/023,838 →
Publication:
US US20110258366A1
High Speed Interface for Daisy-Chained Devices
Application:
13/914,126 →
Publication:
US US20130275628A1
Serially Connected Memory Having Subdivided Data Interface
Write Scheme in a Phase Change Memory
Application:
13/636,547 →
Publication:
US US20130033929A1
Method and Apparatus for Concurrently Reading a Plurality of Memory Devices Using a Single Buffer
Application:
13/102,310 →
Publication:
US US20110276775A1
Multi-Chip Package with Pillar Connection
Application:
14/163,499 →
Publication:
US US20140141566A1
Semiconductor Device with Through-Silicon Vias
Semiconductor Device with Configurable Through-Silicon Vias
Multipage Program Scheme for Flash Memory
Method, System and Apparatus for Multi-Level Processing
Application:
13/239,977 →
Publication:
US US20120096292A1
Method and Apparatus for Sharing Internal Power Supplies in Integrated Circuit Devices
Connection of Multiple Semiconductor Memory Devices with Chip Enable Function
Application:
13/588,195 →
Publication:
US US20130094271A1
Power Saving Methods for Use in a System of Serially Connected Semiconductor Devices
Application:
13/425,801 →
Publication:
US US20130128678A1
Memory System and Method Using Stacked Memory Device Dice
Solid State Drive Memory System
Voltage Regulation for 3D Packages and Method of Manufacturing Same
Memory System with a Layer Comprising a Dedicated Redundancy Area
Flash Memory System
Method and Apparatus for Connecting Inlaid Chip into Printed Circuit Board
Application:
13/621,887 →
Publication:
US US20130068509A1
Cpu with Stacked Memory
Flash Memory Module and Memory Subsystem
Package Having Stacked Memory Dies with Serially Connected Buffer Dies
Application:
13/675,163 →
Publication:
US US20130119542A1
Device Selection Schemes in Multi Chip Package Nand Flash Memory System
Method and Apparatus for Connecting Memory Dies to Form a Memory System
Ring Topology Status Indication
Application:
13/903,418 →
Publication:
US US20130326090A1
Apparatus and Methods for Carrying Out Operations in a Non-Volatile Memory Cell Having Multiple Memory States
Application:
13/799,765 →
Publication:
US US20130343125A1
Storage System Having a Heatsink
Application:
13/800,897 →
Publication:
US US20140036435A1
Flash Memory Controller Having Dual Mode Pin-Out
Split Block Decoder for a Nonvolatile Memory Device
Power Saving in Wireless Network Entities
Integrated Erase Voltage Path for Multiple Cell Substrates in Nonvolatile Memory Devices
Flash Memory Controller Having Multi Mode Pin-Out
Application:
13/836,113 →
Publication:
US US20140122777A1
Pll Locking Control in Daisy Chained Memory System
Method and System for Programming Non-Volatile Memory with Junctionless Cells
Nand Flash Memory with Vertical Cell Stack Structure and Method for Manufacturing Same
Nonvolatile Memory with Split Substrate Select Gates and Heirarchical Bitline Configuration
Structure and Method for Manufacture of Memory Device with Thin Silicon Body
Lithography-friendly Local Read Circuit for NAND Flash Memory Devices and Manufacturing Method Thereof
Asynchronous Bridge Chip
Application:
14/180,582 →
Publication:
US US20140293705A1
U-Shaped Common-Body Type Cell String
Structure and Method of Manufacturing a Stacked Memory Array for Junction-Free Cell Transistors
Application:
13/969,058 →
Publication:
US US20150048434A1
System and Method of Operation for High Capacity Solid-State Drive
Application:
14/102,063 →
Publication:
US US20150161038A1
Through Semiconductor via Structure with Reduced Stress Proximity Effect
Application:
14/312,052 →
Publication:
US US20150021773A1
Vertical Gate Stacked Nand and Row Decoder for Erase Operation
Cell Array with a Manufacturable Select Gate for a Nonvolatile Semiconductor Memory Device
Frequency Division Multiplexing System with Selectable Rate
Local Area Network for Distributing Data Communication, Sensing and Control Signals
Application:
14/064,442 →
Publication:
US US20140050228A1
Network for Telephony and Data Communication
A Telephone Outlet for Implementing a Local Area Network Over Telephone Lines and a Local Area Network Using Such Outlets
Network Combining Wired and Non-Wired Segments
Network Combining Wired and Non-Wired Segments
Network Combining Wired and Non-Wired Segments
Network Combining Wired and Non-Wired Segments
Network Combining Wired and Non-Wired Segments
Network Combining Wired and Non-Wired Segments
System for Transmission Line Termination by Signal Cancellation
Application:
14/053,828 →
Publication:
US US20140035615A1
Telephone Outlet with Packet Telephony Adapter, and a Network Using Same
Application:
14/280,844 →
Publication:
US US20140254585A1
Outlet with Analog Signal Adapter, a Method for Use Thereof and a Network Using Said Outlet
Application:
12/986,539 →
Publication:
US US20110096778A1
Local Area Network of Serial Intelligent Cells
Local Area Network of Serial Intelligent Cells
Local Area Network of Serial Intelligent Cells
Local Area Network of Serial Intelligent Cells
Method and System for Providing Dc Power on Local Telephone Lines
Application:
14/279,955 →
Publication:
US US20140321636A1
Telephone system having multiple distinct sources and accessories therefor
Application:
11/712,508 →
Publication:
US US20070153836A1
Modular Outlet
Application:
14/083,668 →
Publication:
US US20140170902A1
Addressable Outlet, and a Network Using the Same
Application:
12/016,324 →
Publication:
US US20080175256A1
Outlet Add-on Module
Application:
14/057,724 →
Publication:
US US20140093057A1
Device, Method and System for Estimating the Termination to a Wired Transmission-Line Based on Determination of Characteristic Impedance
Application:
13/784,361 →
Publication:
US US20130176043A1
Method for Erasing Memory Cells in a Flash Memory Device Using a Positive Well Bias Voltage and a Negative Word Line Voltage
Dispersion Tolerant Optical System and Method
Application:
13/951,058 →
Publication:
US US20140219664A1
Position Determination of Mobile Stations in a Wireless Network
Position Determination of Mobile Stations in a Wireless Network
Intelligent Video, Data Streaming and Access to Distributed Resources in a Wireless Network
Distributed Network Management Hierarchy in a Multi-Station Communication Network
Integrated Circuit Chip Having Anti-Moisture-Absorption Film at Edge Thereof and Method of Forming Anti-Moisture-Absorption Film
Patent:
46,549 →
Application:
14/025,203 →
Semiconductor Device Having Metal Lines with Slits
Duty Cycle Correction Circuit of Delay Locked Loop and Delay Locked Loop Having the Duty Cycle Correction Circuit
Patent:
45,247 →
Application:
13/405,703 →
Semiconductor Devices Having a Contact Plug and Fabrication Methods Thereof
Application:
13/593,655 →
Dynamic Traffic Rearrangement and Restoration for Mpls Networks with Differentiated Services Capabilities
Application:
14/030,194 →
Publication:
US US20140016652A1
Multi-Hazard Alarm System Using Selectable Power-Level Transmission and Localization
Application:
13/867,158 →
Publication:
US US20130237182A1
Non-Volatile Memory Devices and Control and Operation Thereof
Circuit, System and Method for Selectively Turning Off Internal Clock Drivers
Sequential Pulse Deposition
Application:
13/037,113 →
Publication:
US US20110212628A1
A Vertical Transistor Having a Vertical Gate Structure Having a Top or Upper Surface Defining a Facet Formed Between a Vertical Source and a Vertical Drain.
Integrated Circuitry
Application:
12/612,032 →
Mixed Composition Interface Layer and Method of Forming
Application:
13/293,778 →
Publication:
US US20120120549A1
Network Architecture for Data Communication
Method, Apparatus, Signals, and Medium for Managing Power in a Hybrid Vehicle
Method and System for Multiphase Current Sensing
Patent:
45,880 →
Application:
13/774,415 →
Method and Apparatus for Starting an Internal Combustion Engine
Apparatus and Method for Delivering Power in a Hybrid Vehicle
Programmable gate controller system and method
Method, Apparatus, Signals and Media, for Selecting Operating Conditions of a Genset
Method and Apparatus for Starting an Engine in a Hybrid Vehicle
Single Chip Frame Buffer and Graphics Accelerator
Patent:
40,326 →
Application:
10/264,013 →
Single Chip Frame Buffer and Graphics Accelerator
Patent:
41,565 →
Application:
11/872,353 →
Single Chip Frame Buffer and Graphics Accelerator
Patent:
44,589 →
Application:
12/819,467 →
Self-Timed Circuit Control Device and Method
Patent:
5,729,160 →
Application:
08/277,580 →
Delayed Locked Loop Implementation in a Synchronous Dynamic Random Access Memory
Patent:
6,067,272 →
Application:
08/996,095 →
Delay Locked Loop Implementation in a Synchronous Dynamic Random Access Memory
Delayed Locked Loop Implementation in a Synchronous Dynamic Random Access Memory
Patent:
6,205,083 →
Application:
09/392,088 →
Delayed locked loop implementation in a synchronous dynamic random access memory
Delayed Locked Loop Implementation in a Synchronous Dynamic Random Access Memory
Delayed Locked Loop Implementation in a Synchronous Dynamic Random Access Memory
Delay locked loop implementation in a synchronous dynamic random access memory
Delay Locked Loop Implementation in a Synchronous Dynamic Random Access Memory
Delay Locked Loop Implementation in a Synchronous Dynamic Random Access Memory
Delay Locked Loop Implementation in a Synchronous Dynamic Random Access Memory
Patent:
5,796,673 →
Application:
08/319,042 →
Flexible Dram Array
Patent:
5,712,823 →
Application:
08/597,510 →
Flexible Dram Array
Patent:
5,903,511 →
Application:
08/999,002 →
Flexible Dram Array
Patent:
5,724,286 →
Application:
08/355,957 →
Method of Multilevel Dram Sense and Restore
Patent:
5,612,912 →
Application:
08/584,887 →
Method of Multilevel Dram Sense and Restore
Patent:
5,532,955 →
Application:
08/366,921 →
Built in Access Time Comparator
Patent:
5,844,916 →
Application:
08/429,544 →
Edge Triggered Set-Reset Flip-Flop (Srff)
Patent:
5,633,607 →
Application:
08/430,228 →
Integrated Circuit Test Head
Patent:
5,834,946 →
Application:
08/961,412 →
Digital Delay Line for a Reduced Jitter Digital Delay Lock Loop
Patent:
5,777,501 →
Application:
08/638,809 →
Power-Up/Power-Down Reset Circuit for Low Voltage Interval
Patent:
5,686,848 →
Application:
08/638,810 →
Command Encoded Delayed Clock Generator
Patent:
5,652,733 →
Application:
08/638,812 →
Power Savings Technique in Solid State Integrated Circuits
Patent:
5,973,552 →
Application:
08/743,348 →
Column Redundancy in Semiconductor Memories
Patent:
6,141,268 →
Application:
09/348,314 →
Column Redundancy in Semiconductor Memories
Patent:
5,959,903 →
Application:
08/904,153 →
Current Mode Digital to Analogue Converter
Patent:
5,870,049 →
Application:
08/838,168 →
Digital delay locked loop
Patent:
6,337,590 →
Application:
09/572,954 →
Digital Delay Locked Loop
Patent:
6,087,868 →
Application:
09/069,140 →
Bist Memory Test System
Patent:
6,182,257 →
Application:
09/000,968 →
Bi-Directional Data Bus Scheme with Optimized Read and Write Characters
Patent:
6,134,153 →
Application:
09/364,181 →
Bi-Directional Data Bus Scheme with Optimized Read and Write Characters
Patent:
5,982,674 →
Application:
09/163,341 →
Method for Multilevel Dram Sensing
Patent:
6,373,765 →
Application:
09/585,790 →
Multilevel Dram Sensing Analog-to-Digital Converter
Multilevel dram sense amplifier
Patent:
6,373,766 →
Application:
09/585,791 →
Method for Multilevel Dram Sensing
Patent:
6,151,260 →
Application:
09/046,636 →
Graphical Editor for Defining Memory Test Sequences
Patent:
6,029,262 →
Application:
08/978,083 →
Improved Redundancy Selection Circuit for Semiconductor Memories
Patent:
6,144,591 →
Application:
09/193,239 →
Data-Bit Redundancy in Semiconductor Memories
Patent:
5,877,992 →
Application:
09/000,954 →
Address Counter Cell
Patent:
6,075,748 →
Application:
09/399,372 →
Address Counter Cell
Patent:
5,991,226 →
Application:
08/995,991 →
Encryption Processor with Shared Memory Interconnect
Patent:
6,434,699 →
Application:
09/584,930 →
Encryption Processor with Shared Memory Interconnect
Patent:
44,697 →
Application:
13/603,137 →
Semiconductor Memory Asynchronous Pipeline
Semiconductor Memory Asynchronous Pipeline
Semiconductor Memory Asynchronous Pipeline
Semiconductor Memory Asynchronous Pipeline
Semiconductor Memory Asynchronous Pipeline
Semiconductor Memory Asynchronous Pipeline
Semiconductor Memory Asynchronous Pipeline
Semiconductor Memory Asynchronous Pipeline
Regulated Dram Cell Plate and Precharge Voltage Generator
Patent:
6,057,676 →
Application:
09/099,464 →
Process, Voltage, Temperature Independent Switched Delay Compensation Scheme
Process, Voltage, Temperature Independent Switched Delay Compensation Scheme
Process, Voltage, Temperature Independent Switched Delay Compensation Scheme
Process, Voltage, Temperature Independent Switched Delay Compensation Scheme
Process, Voltage, Temperature Independent Switched Delay Compensation Scheme
Patent:
6,327,318 →
Application:
09/106,755 →
High Bandwidth Memory Interface
High Bandwidth Memory Interface
High Bandwidth Memory Interface
High Bandwidth Memory Interface
High Bandwidth Memory Interface
Apparatuses for Synchronous Transfer of Information
High Bandwidth Memory Interface
Column Redundancy Circuit with Reduced Signal Path Delay
Patent:
6,137,735 →
Application:
09/182,495 →
Dual Control Analog Delay Element
Dual Control Analog Delay Element and Related Delay Method
Dual Control Analog Delay Element
Dynamic Content Addressable Memory Cell
Dynamic content addressable memory cell
Patent:
6,320,777 →
Application:
09/533,128 →
Method and Apparatus for Providing a Packet Buffer Random Access Memory
Method and Apparatus for Providing a Packet Buffer Random Access Memory
Method and Apparatus for Providing a Packet Buffer Random Access Memory
Patent:
6,590,901 →
Application:
09/283,778 →
Frequency-Doubling Delay Locked Loop
Frequency-Doubling Delay Locked Loop
Frequency-Doubling Delay Locked Loop
Frequency-Doubling Delay Locked Loop
Frequency-Doubling Delay Locked Loop
Frequency-Doubling Delay Locked Loop
Frequency-Doubling Delay Locked Loop
Patent:
6,441,659 →
Application:
09/562,024 →
System and Method for Multilevel Dram Sensing and Restoring
Method and Apparatus for an Interleaved Non-Blocking Packet Buffer
Patent:
6,711,170 →
Application:
09/386,589 →
Method and Apparatus for Wire Speed Ip Multicast Forwarding
Patent:
6,754,211 →
Application:
09/453,344 →
Method and Apparatus for Generating Forward Overrides in a Packet Switch
Patent:
6,661,791 →
Application:
09/473,074 →
Link Aggregation
Link Aggregation
Patent:
6,765,866 →
Application:
09/516,001 →
Multi-Stage Lookup for Translating Between Signals of Different Bit Lengths
Multi-stage lookup for translating between signals of different bit lengths
Patent:
6,384,750 →
Application:
09/533,724 →
Port Packet Queuing
Port Packet Queuing
Port Packet Queuing
Port Packet Queuing
Patent:
7,236,489 →
Application:
09/559,190 →
Matchline Sense Circuit and Method
Matchline Sense Circuit and Method
Matchline Sense Circuit and Method
Method and Apparatus for Providing Input Back Pressure in an Output Buffered Switch
Patent:
6,856,595 →
Application:
09/574,621 →
Searchline Control Circuit and Power Reduction Method
Searchline Control Circuit and Power Reduction Method
Method and Apparatus for Simultaneous Differential Data Sensing and Capture in a High Speed Memory
Method and Apparatus for Accelerating Signal Equalization Between a Pair of Signal Lines
Method and Apparatus for Synchronization of Row and Column Access Operations
Method and Apparatus for Synchronization of Row and Column Access Operations
Method and Apparatus for Synchronization of Row and Column Access Operations
Method and Apparatus for Synchronization of Row and Column Access Operations
Method and Apparatus for Synchronization of Row and Column Access Operations
Method and Apparatus for Synchronization of Row and Column Access Operations
Method and Apparatus for Synchronization of Row and Column Access Operations
Method and Circuit for Accelerating Redundant Address Matching
High Speed Dram Architecture with Uniform Access Latency
High Speed Dram Architecture with Uniform Access Latency
High Speed Dram Architecture with Uniform Access Latency
High Speed Dram Architecture with Uniform Access Latency
High Speed Dram Architecture with Uniform Access Latency
High Speed Dram Architecture with Uniform Access Latency
High Speed Dram Architecture with Uniform Access Latency
Method and Apparatus for Reducing Pool Starvation in a Shared Memory Switch
Method and Apparatus for Reducing Pool Starvation in a Shared Memory Switch
Method and Apparatus for Reducing Pool Starvation in a Shared Memory Switch
Method and Apparatus for Reducing Pool Starvation in a Shared Memory Switch
Method and Apparatus for Reducing Pool Starvation in a Shared Memory Switch
Patent:
7,007,071 →
Application:
09/624,276 →
Method and Apparatus for Searching a Filtering Database with One Search Operation
Method and Apparatus for Searching a Filtering Database with One Search Operation
Patent:
6,633,567 →
Application:
09/652,196 →
Method and Apparatus for Accelerating Retrieval of Data from a Memory System with Cache by Reducing Latency
Method and Apparatus for Accelerating Retrieval of Data from a Memory System with Cache by Reducing Latency
Method and Apparatus for Reducing Latency in a Memory System
Method and Apparatus for Selectively Disabling Logic in a Semiconductor Device
Patent:
6,434,077 →
Application:
09/804,988 →
Bitline Precharge
Bitline Precharge
Cascaded Charge Pump Power Supply
Content Addressable Memory Cell
Content Addressable Memory Cell Having Improved Layout
Content Addressable Memory Cell Having Improved Layout
Digitally Controlled Pulse Width Adjusting Circuit
Patent:
6,538,465 →
Application:
10/084,620 →
Column Redundancy for Content Addressable Memory
Priority Encoder Circuit and Method for Content Addressable Memory
Matchline Sensing for Content Addressable Memories
Low Power Content Addressable Memory Architecture
Patent:
6,584,003 →
Application:
10/134,753 →
Trunking in a Matrix
Trunking in a Matrix
Trunking in a Matrix
Method and System for Packet Encryption
Method and System for Packet Processing
Method and System for Packet Encryption
Method and Apparatus for Selecting an Encryption Integrated Circuit Operating Mode
Method and Apparatus for Selecting an Encryption Integrated Circuit Operating Mode
Method and Apparatus for Switchably Selecting an Integrated Circuit Operating Mode
Patent:
6,466,048 →
Application:
09/862,339 →
Programmable Interconnect for Semiconductor Devices
Patent:
6,559,544 →
Application:
10/107,821 →
Congestion Level Management in a Network Device
Congestion Management in a Network
Method and Apparatus for Reordering Entries in a Multi Probe Lookup
Sorting Method and Apparatus Using a Cam
Sorting Method and Apparatus Using a Cam
Sorting Method and Apparatus Using a Cam
Content Addressable Memory Architecture
Content Addressable Memory Architecture
Content Addressable Memory Architecture
Method and Apparatus for Interconnecting Content Addressable Memory Devices
Method and Apparatus for Interconnecting Content Addressable Memory Devices
Method for allocating processor resources and system for encrypting data
Method and Structure for Reducing Noise Effects in Content Addressable Memories
Patent:
6,563,727 →
Application:
10/208,011 →
Method and Apparatus for Replacing Defective Rows in a Semiconductor Memory Array
Block Programmable Priority Encoder in a Cam
Block Programmable Priority Encoder in a Cam
Patent:
43,552 →
Application:
12/709,198 →
Wide Frequency Range Delay Locked Loop
Wide Frequency Range Delay Locked Loop
Wide Frequency Range Delay Locked Loop
Wide Frequency Range Delay Locked Loop
Wide Frequency Range Delay Locked Loop
Synchronization Circuit and Method with Transparent Latches
Double Data Rate Output Latch for Static Ram Device Has Edge-Triggered Flip-Flop to Output Ddr Signal to Synchronize with a Second Clock Signal
Double Data Rate Output Circuit and Method
Double Data Rate Output Circuit
Synchronization Circuit and Method with Transparent Latches
Bi-Directional Amplifier and Method for Accelerated Bus Line Communication
Arrayed Processing Element Redundancy Architecture
Method and Apparatus for Performing Repeated Content Addressable Memory Searches
Timing Vernier Using a Delay Locked Loop
Timing Vernier Using a Delay Locked Loop
Timing Vernier Using a Delay Locked Loop
Timing Vernier Using a Delay Locked Loop
Timing Vernier Using a Delay Locked Loop
Timing Vernier Using a Delay Locked Loop
Timing Vernier Using a Delay Locked Loop
Start Up Circuit for Delay Locked Loop
Initialization Circuit for Delay Locked Loop
Initialization Circuit for Delay Locked Loop
Start Up Circuit for Delay Locked Loop
Hybrid Content Addressable Memory
Mismatch-Dependent Power Allocation Technique for Match-Line Sensing in Content-Addressable Memories
Low Power Match-Line Sensing Circuit
Low Power Match-Line Sensing Circuit
Mismatch-Dependent Power Allocation Technique for Match-Line Sensing in Content-Addressable Memories
Compare Circuit for a Content Addressable Memory Cell
Compare Circuit for a Content Addressable Memory Cell
Ternary Cam Cell for Reduced Matchline Capacitance
Charge Pump for Pll/Dll
Charge Pump for Pll/Dll
Charge Pump for Pll/Dll
Charge Pump for Pll/Dll
Charge Pump for Pll/Dll
Charge Pump for Pll/Dll
High Output Impedance Charge Pump for Pll/Dll
Clock Logic Domino Circuits for High-Speed and Energy Efficient Microprocessor Pipelines
Delay Locked Loop Circuit and Method
Method and Apparatus for Initializing a Delay Locked Loop
Delay Locked Loop Circuit and Method
Patent:
43,947 →
Application:
13/105,749 →
Delay Locked Loop Circuit and Method
Voltage Down Converter for High Speed Memory
Voltage Down Converter for High Speed Memory
Voltage Down Converter for High Speed Memory
Voltage Down Converter for High Speed Memory
Semiconductor Integrated Circuit Having Current Leakage Reduction Scheme
Semiconductor Integrated Circuit Having Current Leakage Reduction Scheme
Power Up Circuit with Low Power Sleep Mode Operation
Power Up Circuit with Low Power Sleep Mode Operation
Flash Memory Device with Data Output Control
Method and System for Accessing a Flash Memory Device
Method and System for Accessing a Flash Memory Device
Multiple Independent Serial Link Memory
Semiconductor Integrated Circuit Having Low Power Consumption with Self-Refresh
Dynamic Random Access Memory Device and Method for Self-Refreshing Memory Cells
Dynamic Random Access Memory Device and Method for Self-Refreshing Memory Cells
Dynamic Random Access Memory Device and Method for Self-Refreshing Memory Cells
Dynamic Random Access Memory Device and Method for Self-Refreshing Memory Cells
Power Managers for an Integrated Circuit
Power Managers for an Integrated Circuit
Power Managers for an Integrated Circuit
Power Managers for an Integrated Circuit
Power Managers for an Integrated Circuit
Managing Power on Integrated Circuits Using Power Islands
Low Leakage and Data Retention Circuitry
Low Leakage and Data Retention Circuitry
Low Leakage and Data Retention Circuitry
Low Leakage and Data Retention Circuitry
Low Leakage and Data Retention Circuitry
Low Leakage and Data Retention Circuitry
Systems and Methods for Minimizing Static Leakage of an Integrated Circuit
Systems and Methods for Minimizing Static Leakage of an Integrated Circuit
Systems and Methods for Minimizing Static Leakage of an Integrated Circuit
Systems and Methods for Minimizing Static Leakage of an Integrated Circuit
Systems and Methods for Minimizing Static Leakage of an Integrated Circuit
Phase-Locked Loop Circuitry Using Charge Pumps with Current Mirror Circuitry
Phase-Locked Loop Circuitry Using Charge Pumps with Current Mirror Circuitry
Integrated Circuit with Signal Bus Formed by Cell Abutment of Logic Cells
Integrated Circuit with Signal Bus Formed by Cell Abutment of Logic Cells
Apparatus and Method for Self-Refreshing Dynamic Random Access Memory Cells
Apparatus and Method for Self-Refreshing Dynamic Random Access Memory Cells
Apparatus and Method for Self-Refreshing Dynamic Random Access Memory Cells
Apparatus and Method for Self-Refreshing Dynamic Random Access Memory Cells
Asic Design Using Clock and Power Grid Standard Cell
Phase-Locked Loop Filter Capacitance with a Drag Current
Sram Leakage Reduction Circuit
Sram Leakage Reduction Circuit
Sram Leakage Reduction Circuit
Voltage Level Shifter Circuit
Voltage Level Shifter Circuit
Non-Volatile Memory Bank and Page Buffer Therefor
Non-Volatile Memory Serial Core Architecture
Flash Memory System Control Scheme
Non-Volatile Semiconductor Memory with Page Erase
Non-Volatile Semiconductor Memory with Page Erase
Non-Volatile Semiconductor Memory with Page Erase
Non-Volatile Semiconductor Memory with Page Erase
Non-Volatile Semiconductor Memory with Page Erase
Flash Multi-Level Threshold Distribution Scheme
Flash Multi-Level Threshold Distribution Scheme
Flash Multi-Level Threshold Distribution Scheme
Flash Multi-Level Threshold Distribution Scheme
Flash Multi-Level Threshold Distribution Scheme
Low Power Memory Architecture
Low Power Memory Architecture
Dynamic Random Access Memory Device and Method for Self-Refreshing Memory Cells with Temperature Compensated Self-Refresh
Dynamic Random Access Memory Device and Method for Self-Refreshing Memory Cells with Temperature Compensated Self-Refresh
Dynamic Random Access Memory Device and Method for Self-Refreshing Memory Cells with Temperature Compensated Self-Refresh
Dynamic Random Access Memory Device and Method for Self-Refreshing Memory Cells with Temperature Compensated Self-Refresh
Dynamic Random Access Memory Device and Method for Self-Refreshing Memory Cells with Temperature Compensated Self-Refresh
Dynamic Random Access Memory with Fully Independent Partial Array Refresh Function
Dynamic Random Access Memory with Fully Independent Partial Array Refresh Function
Dynamic Random Access Memory with Fully Independent Partial Array Refresh Function
Dynamic Random Access Memory with Fully Independent Partial Array Refresh Function
Flash Memory Program Inhibit Scheme
Flash Memory Program Inhibit Scheme
Flash Memory Program Inhibit Scheme
Flash Memory Program Inhibit Scheme
Method and Apparatus for Integrated Circuit Design with a Software Tool
Method and Apparatus for Design of Integrated Circuits
Method and Apparatus for Integrated Circuit Design with Library Cells
A Double Data Rate Converter Circuit Includes a Delay Locked Loop for Providing the Plurality of Clock Phase Signals
Apparatus and Method for Interfacing to a Memory
Synchronous Memory Read Data Capture
Synchronous Memory Read Data Capture
Apparatus and Method for Establishing Device Identifiers for Serially Interconnected Devices
Data Flow Control in Multiple Independent Port
Data Flow Control in Multiple Independent Port
Data Flow Control in Multiple Independent Port
Pulse Counter with Clock Edge Recovery
Apparatus and Method for Producing Ids for Interconnected Devices of Mixed Type
Apparatus and Method for Producing Ids for Interconnected Devices of Mixed Type
Asynchronous Id Generation
Daisy Chain Cascade Configuration Recognition Technique
Hybrid Solid-State Memory System Having Volatile and Non-Volatile Memory
Hybrid Solid-State Memory System Having Volatile and Non-Volatile Memory
Hybrid Solid-State Memory System Having Volatile and Non-Volatile Memory
Independent Link and Bank Selection
Independent Link and Bank Selection
Independent Link and Bank Selection
Independent Link and Bank Selection
Memory with Output Control
Memory with Output Control
Memory with Output Control
Memory with Output Control
Memory with Output Control
Packet Based Id Generation for Serially Interconnected Devices
Error Correction Scheme for Memory
Error Correction Scheme for Memory
Circuit and Method for Testing Multi-Device Systems
Circuit and Method for Testing Multi-Device Systems
Circuit and Method for Testing Multi-Device Systems
Circuit and Method for Testing Multi-Device Systems
Memory System and Method with Serial and Parallel Modes
Memory System and Method with Serial and Parallel Modes
Address Assignment and Type Recognition of Serially Interconnected Memory Devices of Mixed Type
Circuit for Clamping Current in a Charge Pump
Circuit for Clamping Current in a Charge Pump
Circuit for Clamping Current in a Charge Pump
Apparatus and Method for Capturing Serial Input Data
Delay Locked Loop Circuit
Delay Locked Loop Circuit
Delay Locked Loop Circuit
Phase Detector Circuit and Method Therefor
Decoding Control with Address Transition Detection in Page Erase Function
Decoding Control with Address Transition Detection in Page Erase Function
System and Method of Page Buffer Operation for Memory Devices
Apparatus and Method for Producing Device Identifiers for Serially Interconnected Devices of Mixed Type
Apparatus and Method for Producing Device Identifiers for Serially Interconnected Devices of Mixed Type
Phase Shifting in Dll/Pll
Apparatus and Method for Producing Device Identifiers for Serially Interconnected Devices of Mixed Type
Apparatus and Method for Producing Device Identifiers for Serially Interconnected Devices of Mixed Type
Non-Volatile Memory with Dynamic Multi-Mode Operation
Non-Volatile Memory with Dynamic Multi-Mode Operation
Non-Volatile Memory with Dynamic Multi-Mode Operation
Non-Volatile Memory with Dynamic Multi-Mode Operation
Non-Volatile Memory with Dynamic Multi-Mode Operation
Simplified Bias Circuitry for Differential Buffer Stage with Symmetric Loads
Simplified Bias Circuitry for Differential Buffer Stage with Symmetric Loads
Bias Generator Providing for Low Power, Self-Biased Delay Element and Delay Line
Bias Generator Providing for Low Power, Self-Biased Delay Element and Delay Line
Voltage Level Shifter and Buffer Using Same
Voltage Level Shifter and Buffer Using Same
Source Side Asymmetrical Precharge Programming Scheme
Source Side Asymmetrical Precharge Programming Scheme
Source Side Asymmetrical Precharge Programming Scheme
Apparatus and Method for Producing Identifiers Regardless of Mixed Device Type in a Serial Interconnection
Apparatus and Method for Producing Identifiers Regardless of Mixed Device Type in a Serial Interconnection
Apparatus and Method for Communicating with Semiconductor Devices of a Serial Interconnection
Apparatus and Method for Communicating with Semiconductor Devices of a Serial Interconnection
Modular Command Structure for Memory and Memory System
Apparatus and Method for Identifying Device Type of Serially Interconnected Devices
Methods and Apparatus for Clock Signal Synchronization in a Configuration of Series-Connected Semiconductor Devices
Methods and Apparatus for Clock Signal Synchronization in a Configuration of Series-Connected Semiconductor Devices
Circuit and Method for Glitch Correction
Dynamic Impedance Control for Input/Output Buffers
Dynamic Impedance Control for Input/Output Buffers
Memory with Data Control
Storage of Data in Memory via Packet Strobing
Apparatus and Method of Page Program Operation for Memory Devices with Mirror Back-Up of Data
Apparatus and Method of Page Program Operation for Memory Devices with Mirror Back-Up of Data
Apparatus and Method of Page Program Operation for Memory Devices with Mirror Back-Up of Data
Memory System Having Incorrupted Strobe Signals
Memory System Having Incorrupted Strobe Signals
Dynamic Random Access Memory and Boosted Voltage Producer Therefor
Dynamic Random Access Memory and Boosted Voltage Producer Therefor
Multi-Level Cell Access Buffer with Dual Function
Multi-Level Cell Access Buffer with Dual Function
Multi-Level Cell Access Buffer with Dual Function
Multi-Level Cell Access Buffer with Dual Function
Pre-Charge Voltage Generation and Power Saving Modes
Pre-Charge Voltage Generation and Power Saving Modes
Pre-Charge Voltage Generation and Power Saving Modes
Reduced Pin Count Interface
Reduced Pin Count Interface
Partial Block Erase Architecture for Flash Memory
Non-Volatile Semiconductor Memory Having Multiple External Power Supplies
Non-Volatile Semiconductor Memory Having Multiple External Power Supplies
Patent:
8,300,471 →
Application:
13/096,874 →
Non-Volatile Semiconductor Memory Having Multiple External Power Supplies
Non-Volatile Semiconductor Memory Having Multiple External Power Supplies
Single-Strobe Operation of Memory Devices
Single-Strobe Operation of Memory Devices
Single-Strobe Operation of Memory Devices
Ring-Of-Clusters Network Topologies
Methods and Systems for Failure Isolation and Data Recovery in a Configuration of Series-Connected Semiconductor Devices
Methods and Systems for Failure Isolation and Data Recovery in a Configuration of Series-Connected Semiconductor Devices
Scalable Memory System
Scalable Memory System
Semiconductor Device and Method for Selection and De-Selection of Memory Devices Interconnected in Series
Clock Mode Determination in a Memory System
Clock Mode Determination in a Memory System
Clock Mode Determination in a Memory System
Apparatus and Method for Modeling Coarse Stepsize Delay Element and Delay Locked Loop Using Same
Apparatus and Method for Modeling Coarse Stepsize Delay Element and Delay Locked Loop Using Same
System and Method of Operating Memory Devices of Mixed Type
System and Method of Operating Memory Devices of Mixed Type
Data Channel Test Apparatus and Method Thereof
Data Channel Test Apparatus and Method Thereof
Nonvolatile Semiconductor Memory Device
Nonvolatile Memory Having Non-Power of Two Memory Capacity
Memory Controller with Flexible Data Alignment to Clock
Memory Controller with Flexible Data Alignment to Clock
Apparatus and Method for Using a Page Buffer of a Memory Device as a Temporary Cache
Method for Stacking Serially-Connected Integrated Circuits and Multi-Chip Device Made from Same
Method for Stacking Serially-Connected Integrated Circuits and Multi-Chip Device Made from Same
Method for Stacking Serially-Connected Integrated Circuits and Multi-Chip Device Made from Same
Hierarchical Common Source Line Structure in Nand Flash Memory
Hierarchical Common Source Line Structure in Nand Flash Memory
Hierarchical Common Source Line Structure in Nand Flash Memory
Multiple Bit Per Cell Non Volatile Memory Apparatus and System Having Polarity Control and Method of Programming Same
Multiple-Bit Per Cell (Mbc) Non-Volatile Memory Apparatus and System Having Polarity Control and Method of Programming Same
Multiple-Bit Per Cell (Mbc) Non-Volatile Memory Apparatus and System Having Polarity Control and Method of Programming Same
Mulitple-Bit Per Cell (Mbc) Non-Volatile Memory Apparatus and System Having Polarity Control and Method of Programming Same
Dual Function Compatible Non-Volatile Memory Device
Dual Function Compatible Non-Volatile Memory Device
Dual Function Compatible Non-Volatile Memory Device
Dual Function Compatible Non-Volatile Memory Device
Non-Volatile Semiconductor Memory Device with Power Saving Feature
Non-Volatile Semiconductor Memory Device with Power Saving Feature
Non-Volatile Semiconductor Memory Device with Power Saving Feature
Nand Flash Memory Having Multiple Cell Substrates
Nand Flash Memory Having Multiple Cell Substrates
Clock Reproducing and Timing Method in a System Having a Plurality of Devices
Operational Mode Control in Serial-Connected Memory Based on Identifier
Patent:
44,926 →
Application:
13/774,477 →
Power Supplies in Flash Memory Devices and Systems
Power Supplies in Flash Memory Devices and Systems
Power Supplies in Flash Memory Devices and Systems
Selective Broadcasting of Data in Series Connected Devices
Apparatus and Method for Identifying Device Types of Series-Connected Devices of Mixed Type
Apparatus and Method for Identifying Device Types of Series-Connected Devices of Mixed Type
Non-Volatile Memory Device Having Configurable Page Size
Non-Volatile Memory Device Having Configurable Page Size
Non-Volatile Memory Device Having Configurable Page Size
System Having One or More Memory Devices
Data Storage and Stackable Configurations
Flexible Memory Operations in Nand Flash Devices
Flexible Memory Operations in Nand Flash Devices
Cache Filtering Method and Apparatus
Mixed Data Rates in Memory Devices and Systems
Serial-Connected Memory System with Duty Cycle Correction
Serial-Connected Memory System with Output Delay Adjustment
Data Mirroring in Serial-Connected Memory System
Bridge Device Architecture for Connecting Discrete Memory Devices to a System
Composite Memory Having a Bridging Device for Connecting Discrete Memory Devices to a System
Semiconductor Device with Main Memory Unit and Auxiliary Memory Unit Requiring Preset Operation
Device and Method for Transferring Data to a Non-Volatile Memory Device
System Including a Plurality of Encapsulated Semiconductor Chips
Termination Circuit for on-Die Termination
Termination Circuit for on-Die Termination
Stacked Semiconductor Devices Including a Master Device
Stacked Semiconductor Devices Including a Master Device
Stacked Semiconductor Devices Including a Master Device
Nand Flash Architecture with Multi-Level Row Decoding
Configurable Module and Memory Subsystem
Configurable Module and Memory Subsystem
Bridge Device Architecture for Connecting Discrete Memory Devices to a System
Bridge Device Architecture for Connecting Discrete Memory Devices to a System
Bridging Device Having a Configurable Virtual Page Size
Simultaneous Read and Write Data Transfer
Bridging Device Having a Frequency Configurable Clock Domain
Using Interrupted Through-Silicon-Vias in Integrated Circuits Adapted for Stacking
Using Interrupted Through-Silicon-Vias in Integrated Circuits Adapted for Stacking
Semiconductor Memory with Multiple Wordline Selection
Package-Level Integrated Circuit Connection Without Top Metal Pads or Bonding Wire
System and Method Providing Interoperability Between Cellular and Other Wireless Systems
Reconfiguring Through Silicon Vias in Stacked Multi-Die Packages
Phase Change Memory Word Line Driver
Multi-Chip Package with Offset Die Stacking
Memory System Having a Plurality of Serially Connected Devices
Method of Configuring Non-Volatile Memory for a Hybrid Disk Drive
Method of Configuring Non-Volatile Memory for a Hybrid Disk Drive
Memory Programming Using Variable Data Width
Phase-Change Memory with Multiple Polarity Bits Having Enhanced Endurance and Error Tolerance
Phase-Change Memory with Multiple Polarity Bits Having Enhanced Endurance and Error Tolerance
High-Speed Interface for Daisy-Chained Devices
Semiconductor Memory Device with Sense Amplifier and Bitline Isolation
Semiconductor Memory Device with Sense Amplifier and Bitline Isolation
Multi-Chip Package with Pillar Connection
Multi-Chip Package with Thermal Frame and Method of Assembling
Error Detection and Correction Codes for Channels and Memories with Incomplete Error Characteristics
Error Detection and Correction Codes for Channels and Memories with Incomplete Error Characteristics
Method and Apparatus for Sharing Internal Power Supplies in Integrated Circuit Devices
Independent Write and Read Control in Serially-Connected Devices
Interposer for Stacked Semiconductor Devices
Reduced Noise Dram Sensing
Device Selection Schemes in Multi Chip Package Nand Flash Memory System
Apparatus for the Automated Testing, Calibration and Characterization of Test Adapters
Apparatus for Flexible Deactivation of Word Lines of Dynamic Memory Modules and Method Therefor
Temperature-Dependent Refresh Cycle for Dram
Method of Manufacturing a Semiconductor Device
Patent:
5,723,363 →
Application:
08/537,062 →
Circuit Arrangement and Method for Measuring a Difference in Capacitance Between a First Capacitance C1 and a Second Capacitance C2
Patent:
5,777,482 →
Application:
08/675,590 →
Voltage Detection Circuit and Internal Voltage Clamp Circuit
Patent:
5,847,591 →
Application:
08/829,256 →
Closed-Mold for Led Alphanumeric Displays
Patent:
5,855,924 →
Application:
08/579,535 →
Bipolar Silicon Transistor with Arsenic and Phosphorous Ratio
Patent:
5,965,929 →
Application:
08/623,905 →
Method and Apparatus for Evaluating Internal Film Stress at High Lateral Resolution
Patent:
5,979,244 →
Application:
09/034,517 →
Alphanumeric Display with 21-Dot Matrix Format
Patent:
6,100,858 →
Application:
08/940,703 →
Synchronous Feedback Digital Circuit Having a Minimzed Switching Power Loss
Patent:
6,400,194 →
Application:
09/642,332 →
Method and Apparatus for Determining Interpolated Intermediate Values of a Sampled Signal
Integrated Circuit Configuration for Testing Transistors, and a Semiconductor Wafer Having Such a Circuit Configuration
Method for Efficient Analysis Semiconductor Failures
Patent:
6,553,521 →
Application:
09/511,169 →
System for Testing Fast Synchronous Semiconductor Circuits
Apparatus and Method for Patterning a Semiconductor Wafer
Delay Locked Loop
Measurement Probe for Detecting Electrical Signals in an Integrated Semiconductor Circuit
Tester Apparatus for Electronic Components
Test Apparatus for Parallel Testing a Number of Electronic Components and a Method for Calibrating the Test Apparatus
Method for Determining the Transit Time of Electrical Signals on Printed Circuit Boards Using Automatic Standard Test Equipment
Method for Improving Thermal Process Steps
Patent:
6,706,616 →
Application:
09/914,749 →
Method of Calibrating a Test System for Semiconductor Components, and Test Substrate
Integrated Dynamic Memory and Operating Method
Apparatus for Testing Semiconductor Devices
Method and Probe Card Configuration for Testing a Plurality of Integrated Circuits in Parallel
Test Configuration and Test Method for Testing a Plurality of Integrated Circuits in Parallel
Method for Releasable Contact-Connection of a Plurality of Integrated Semiconductor Modules on a Wafer
Circuit for Testing an Integrated Circuit
Circuit Configuration for Selectively Transmitting Information Items from a Measuring Device to Chips on a Wafer During Chip Fabrication
Asynchronous SRAM compatible memory device using DRAM cell and method for driving the same
Synchronous Sram-Compatible Memory and Method of Driving the Same
Sram-Compatible Memory Device Employing Dram Cells
Multirate Wireless Data Communication System
Patent:
5,706,428 →
Application:
08/615,408 →
Single Sideband Double Quadrature Modulator
Patent:
5,861,781 →
Application:
08/931,370 →
Orthogonal Frequency Division Multiplexing System with Dynamically Scalable Operating Parameters and Method Thereof
Patent:
6,175,550 →
Application:
08/834,684 →
Frequency Division Multiplexing System with Selectable Rate
Frequency Division Multiplexing System with Selectable Rate
Frequency Division Multiplexing System with Selectable Rate
Orthogonal Frequency Division Multiplexing System with Selectable Rate
Patent:
6,563,786 →
Application:
09/224,695 →
Error Screening Based on Code and Control Information Consistency in a Communication System
Patent:
6,662,339 →
Application:
09/464,042 →
Efficient Digital Itu-Compliant Zero-Buffering Dtmf Detection Using the Non-Uniform Discrete Fourier Transform
Efficient Digital Itu-Compliant Zero-Buffering Dtmf Detection Using the Non-Uniform Discrete Fourier Transform
Patent:
6,370,244 →
Application:
09/054,872 →
Paralleled Content Addressable Memory Search Engine
Dual Match-Line, Twin-Cell, Binary-Ternary Cam
Fast Aging Scheme for Search Engine Databases Using a Linear Feedback Shift Register
Binary-Ternary Content Addressable Memory
Patent:
6,362,992 →
Application:
09/684,589 →
Dynamic Linking of Banks in Configurable Content Addressable Memory Systems
Cascading Content Addressable Memory Devices with Programmable Input / Output Connections
Pre-Sense Amplifier for Monolithic Memories
Patent:
5,525,918 →
Application:
08/364,130 →
Staggered Pipeline Access Scheme for Synchronous Random Access MEM0RY
Patent:
5,872,742 →
Application:
09/063,529 →
Staggered Pipeline Access Scheme for Synchronous Random Access Memory
Patent:
5,808,959 →
Application:
08/612,044 →
Determining the Position of a Constant Frequency Interval in a Telecommunication Signal
Patent:
6,937,672 →
Application:
09/515,224 →
Method and Apparatus for Detecting and Correcting Misconvergence of a Blind Equalizer
Patent:
5,694,423 →
Application:
08/692,554 →
Information Transmission System
Patent:
5,636,247 →
Application:
08/407,829 →
Method and Device for Robust Fallback in Data Communication Systems
Method and Apparatus for Reducing Interference in Non-Stationary Subscriber Radio Units Using Flexible Beam Selection
Patent:
6,701,165 →
Application:
09/598,057 →
Method and Apparatus for Controlling Conditional Branch Execution in a Data Processor
Patent:
5,951,678 →
Application:
08/900,796 →
Method and Apparatus for Interfacing a Processor to a Coprocessor for Communicating Register Write Information
Patent:
5,983,338 →
Application:
08/924,508 →
Processing System Having Sequential Address Indicator Signals
Patent:
7,124,281 →
Application:
09/667,122 →
Data Processing System Having Redirecting Circuitry and Method Therefor
Method and Apparatus for Determining Access Permission
Controller and Method for Controlling an Ignition Coil
Instruction for Conditionally Yielding to a Ready Thread Based on Priority Criteria
Selective Misr Data Accumulation During Exception Processing
Address Translation Trace Message Generation for Debug
Program Correlation Message Generation for Debug
Method and Apparatus for Instruction Fetching
Patent:
6,751,724 →
Application:
09/552,118 →
Distributed Serial Control System
Patent:
5,841,360 →
Application:
08/734,921 →
Communications and Control Network Having Multiple Power Supplies
Patent:
6,396,391 →
Application:
09/141,321 →
Local Area Network for Distributing Data Communication, Sensing and Control Signals
Local Area Network for Distributing Data Communication, Sensing and Control Signals
Local Area Network for Distributing Data Communication, Sensing and Control Signals
Local Area Network for Distributing Data Communication, Sensing and Control Signals
Local Area Network for Distributing Data Communication, Sensing and Control Signals
Patent:
6,956,826 →
Application:
09/349,020 →
Networks for Telephony and Data Communication
Network for Telephony and Data Communication
Network for Telephony and Data Communication
Network for Telephony and Data Communication
Network for Telephony and Data Communication
Network for Telephony and Data Communication
Patent:
6,690,677 →
Application:
09/357,379 →
Telephone Outlet for Implementing a Local Area Network Over Telephone Lines and a Local Area Network Using Such Outlets
Telephone Outlet for Implementing a Local Area Network Over Telephone Lines and a Local Area Network Using Such Outlets
Telephone Outlet for Implementing a Local Area Network Over Telephone Lines and a Local Area Network Using Such Outlets
Telephone Outlet for Implementing a Local Area Network Over Telephone Lines and a Local Area Network Using Such Outlets
Telephone Outlet for Implementing a Local Area Network Over Telephone Lines and a Local Area Network Using Such Outlets
Telephone Outlet for Implementing a Local Area Network Over Telephone Lines and a Local Area Network Using Such Outlets
Patent:
6,549,616 →
Application:
09/531,692 →
Network Combining Wired and Non-Wired Segments
Network Combining Wired and Non-Wired Segments
Network Combining Wired and Non-Wired Segments
Network Combining Wired and Non-Wired Segments
Network Combining Wired and Non Wired Segments
Network Combining Wired and Non-Wired Segments
Network Combining Wired and Non-Wired Segments
Patent:
6,842,459 →
Application:
09/552,564 →
Telephone Communication System Over a Single Telephone Line
Telephone Communication System Over a Single Telephone Line
Telephone Communication System Over a Single Telephone Line
Telephone Communication System Over a Single Telephone Line
Telephone Communication System Over a Single Telephone Line
Telephone Communication System Over a Single Telephone Line
Telephone Communication System Over a Single Telephone Line
Telephone Communication System Over a Single Telephone Line
Telephone Communication System Over a Single Telephone Line
Patent:
7,106,721 →
Application:
09/594,765 →
Telephone Communication System and Method Over Local Area Network Wiring
Telephone Communication System and Method Over Local Area Network Wiring
Telephone Communication System and Method Over Local Area Network Wiring
Telephone Communication System and Method Over Local Area Network Wiring
Communication System and Method Over Local Area Network Wiring
Telephone Communication System and Method Over Local Area Network Wiring
Telephone Communication System and Method Over Local Area Network Wiring
Patent:
6,961,303 →
Application:
09/666,856 →
System for Transmission Line Termination by Signal Cancellation
System for Transmission Line Termination by Signal Cancellation
System for Transmission Line Termination by Signal Cancellation
System for Transmission Line Termination by Signal Cancellation
System for Transmission Line Termination by Signal Cancellation
System for Transmission Line Termination by Signal Cancellation
System and Method for Transmission-Line Termination by Signal Cancellation, and Applications Thereof
Method and Telephone Outlet for Allowing Telephone and Data Equipment to Be Connected to a Telephone Line via a Common Connector
Patent:
6,560,319 →
Application:
09/764,342 →
Telephone Outlet with Packet Telephony Adaptor, and a Network Using Same
Telephone Outlet with Packet Telephony Adapter, and a Network Using Same
Telephone Outlet with Packet Telephony Adapter, and a Network Using Same
Telephone Outlet with Packet Telephony Adaptor, and a Network Using Same
Telephone Outlet with Packet Telephony Adapter, and a Network Using Same
Adapter for Mounting a Faceplate of a First Style on to an Electrical Outlet Cavity of a Second Style
Adapter for Mounting a Faceplate of a First Style to an Electrical Outlet Cavity of a Second Style
Adapter for Mounting a Faceplate of a First Style to an Electrical Outlet Cavity of a Second Style
Adapter for Mounting a Faceplate of a First Style to an Electrical Outlet Cavity of a Second Style
Adapter for Mounting a Faceplate of a First Style to an Electrical Outlet Cavity of a Second Style
Adapter for Mounting a Faceplate of a First Style on to an Electrical Outlet Cavity of a Second Style
Patent:
6,927,340 →
Application:
10/451,544 →
Outlet with Analog Signal Adapter, a Method for Use Thereof and a Network Using Said Outlet
Outlet with Analog Signal Adapter, a Method for Use Thereof and a Network Using Said Outlet
Outlet with Analog Signal Adapter, a Method for Use Thereof and a Network Using Said Outlet
Outlet with Analog Signal Adapter, a Method for Use Thereof and a Network Using Said Outlet
Outlet with Analog Signal Adapter, a Method for Use Thereof and a Network Using Said Outlet
Outlet with Analog Signal Adapter, a Method for Use Thereof and a Network Using Said Outlet
Local Area Network of Serial Intelligent Cells
Local Area Network of Serial Intelligent Cells
Local Area Network of Serial Intelligent Cells
Local Area Network of Serial Intelligent Cells
Local Area Network of Serial Intelligent Cells
Local Area Network of Serial Intelligent Cells
Local Area Network of Serial Intelligent Cells
Local Area Network of Serial Intelligent Cells
Local Area Network of Serial Intelligent Cells
Local Area Network of Serial Intelligent Cells
Local Area Network of Serial Intelligent Cells
Local Area Network of Serial Intelligent Cells
Local Area Network of Serial Intelligent Cells
Local Area Network of Serial Intelligent Cells
Local Area Network of Serial Intelligent Cells
Local Area Network of Serial Intellegent Cells
Local Area Network of Serial Intellegent Cells
Local Area Network of Serial Intelligent Cells
Patent:
6,480,510 →
Application:
09/123,486 →
Method and System for Providing Dc Power on Local Telephone Lines
Method and system for providing DC power on local telephone lines
Method and System for Providing Dc Power on Local Telephone Lines
Method and System for Providing Dc Power on Local Telephone Lines
Telephone System Having Multiple Distinct Sources and Accessories Therefor
Telephone System Having Multiple Sources and Accessories Therefor
Telephone System Having Multiple Distinct Sources and Accessories Therefor
Private Telephone Network Connected to More Than One Public Network
Modular Outlet
Modular Outlet
Modular Outlet
Modular Outlet
Modular Outlet
Modular Outlet
Modular Outlet
Modular Outlet
Modular Outlet
An Addressable Outlet for Use in Wired Local Area Network
Addressable Outlet, and a Network Using the Same
Addressable Outlet, and a Network Using the Same
Addressable Outlet, and a Network Using Same
Outlet Add-on Module
Outlet Add-on Module
Outlet Add-on Module
Outlet Add-on Module
Outlet Add-on Module
Outlet Add-on Module
Device, Method and System for Estimating the Termination to a Wired Transmission-Line Based on Determination of Characteristic Impedance
Device, method and system for estimating the termination to a wired transmission-line based on determination of characteristic impedance
Device, Method and System for Estimating the Termination to a Wired Transmission-Line Based on Determination of Characteristic Impedance
Temperature-Dependent Dram Self-Refresh Circuit
Non-Volatile Memory Device with Page Buffer Having Dual Registers and Methods Using the Same
Methods for Programming and Reading Nand Flash Memory Device and Page Buffer Performing the Same
Method for Erasing Memory Cells in a Flash Memory Device Using a Positive Well Bias Voltage and a Negative Word Line Voltage
Word Line Driver in a Hierarchical nor Flash Memory
Temperature Detector in an Integrated Circuit
Temperature Detector in an Integrated Circuit
Temperature Detector in an Integrated Circuit
Method and Apparatus for Reducing Power Consumption in Digital Electronic Circuits
Patent:
36,839 →
Application:
09/212,854 →
Microprocessor Power Control System
Patent:
5,951,689 →
Application:
08/775,629 →
Sleepmode Activation in a Slave Device
Patent:
6,393,572 →
Application:
09/300,902 →
Direct Memory Access Execution Engine with Indirect Addressing of Circular Queues in Addition to Direct Memory Addressing
Patent:
6,463,059 →
Application:
09/205,480 →
Dispersion Tolerant Optical System and Method
Dispersion Tolerant Optical System and Method
Distributed Network Management Hierarchy in a Multi-Station Communication Network
Adaptive Antenna System for Diversity and Interference Avoidance in a Multi-Station Network
Data Loading Circuit for Partial Program of Nonvolatile Semiconductor Memory
Patent:
5,712,818 →
Application:
08/537,615 →
Data Read Circuit for a Nonvolatile Semiconductor Memory
Patent:
5,748,536 →
Application:
08/652,654 →
Method of Making a Dynamic Random Access Memory Device Utilizing Chemical Mechanical Polishing
Patent:
6,271,124 →
Application:
09/395,291 →
Dynamic Random Access Memory Device and Method for Fabricating the Same
Patent:
5,990,510 →
Application:
09/212,053 →
Semiconductor memory device having operation delay function of column address strobe command, and buffer and signal transmission circuit which are applied to the semiconductor memory device
Multi-State Non-Volatile Semiconductor Memory Device
Sdram Having Posted Cas Function
Memory Cell Decoder Not Including a Charge Pump
Integrated Circuit Chip Having Anti-Moisture-Absorption Film at Edge Thereof and Method of Forming Anti-Moisture-Absorption Film
Integrated Circuit Chip Having Anti-Moisture-Absorption Film at Edge Thereof and Method of Forming Anti-Moisture-Absorption Film
Patent:
6,566,735 →
Application:
09/715,372 →
Semiconductor Memory Device
Trench Isolatoin Regions Having Trench Liners with Recessed Ends
Trench isolation structure, semiconductor device having the same, and trench isolation method
Patent:
6,331,469 →
Application:
09/684,822 →
Multilayer Passivation Process for Forming Air Gaps Within a Dielectric Between Interconnections
Data input circuit of semiconductor memory device
Patent:
6,324,119 →
Application:
09/557,619 →
Recessed Gate Electrode Mos Transistors Having a Substantially Uniform Channel Length Across a Width of the Recessed Gate Electrode and Methods of Forming Same
Semiconductor Device Having Metal Lines with Slits
Semiconductor Device Having No Cracks in One or More Layers Underlying a Metal Line Layer
Semiconductor Device Having Metal Lines with Slits
Semiconductor Device Having No Cracks in One or More Layers Underlying a Metal Line Layer and Method of Manufacturing the Same
Semiconductor Device Having No Cracks in One or More Layers Underlying a Metal Line Layer and Method of Manufacturing the Same
Method for Designing Cell Array Layout of Non-Volatile Memory Device
Patent:
6,056,783 →
Application:
08/614,766 →
Contact Structure of Semiconductor Memory Device for Reducing Contact Related Defect and Contact Resistance and Method for Forming the Same
Patent:
6,072,242 →
Application:
09/209,649 →
Circuit and Method of Generating a Boosted Voltage
Devices for Controlling Temperature Indications in Integrated Circuits Using Adjustable Threshold Temperatures
Patent:
6,442,500 →
Application:
09/359,438 →
Methods of Designing and Fabricating Intergrated Circuits Which Take into Account Capacitive Loading by the Intergrated Circuit Potting Material
Patent:
6,028,986 →
Application:
09/052,249 →
Integrated Circuits, and Methods of Fabricating Same, Which Take into Account Capacitive Loading by the Integrated Circuit Potting Material
Patent:
5,808,366 →
Application:
08/694,541 →
Combined Field/Trench Isolation Region Fabrication Methods
Patent:
5,804,491 →
Application:
08/744,436 →
Microelectronic Capacitors Having Tantalum Pentoxide Dielectrics and Oxgen Barriers
Patent:
5,859,760 →
Application:
08/843,799 →
Method of Fabricating Microelectronic Capacitors Having Tantalum Pentoxide Dielectrics and Oxygen Barriers
Patent:
5,763,300 →
Application:
08/709,249 →
Method of Forming a Polycide Gate of a Semiconductor Device
Patent:
5,908,791 →
Application:
08/643,885 →
Methods of Forming Electrically Interconnected Lines Using Ultraviolet Radiation as an Organic Compound Cleaning Agent
Patent:
6,043,165 →
Application:
08/890,578 →
Methods of Fabricating Conductive Lines in Integrated Circuits Using Insulating Sidewall Spacers and Conductive Lines So Fabricated
Patent:
6,066,556 →
Application:
09/184,918 →
Fin-Shaped Capacitor
Patent:
6,078,493 →
Application:
09/083,886 →
Fabricating Method of a Fin Shaped Capacitor
Patent:
5,834,357 →
Application:
08/550,326 →
Method for Forming Integrated Circuit Memory Devices with High and Low Dopant Concentration Regions of Different Diffusivities
Patent:
6,162,672 →
Application:
09/233,412 →
Integrated Circuit Memory Devices with High and Low Dopant Concentration Regions of Different Diffusivities
Patent:
5,969,395 →
Application:
08/854,874 →
Semiconductor Device Having Triple-Well
Patent:
6,225,199 →
Application:
09/348,381 →
Method for Fabricating a Dram Cell Capacitor Including Etching Upper Conductive Layer with Etching Byproduct Forming a Etch Barrier on the Conductive Pattern
Patent:
6,238,970 →
Application:
09/343,353 →
Method of fabricating self-aligning stacked capacitor using electroplating method
Patent:
6,255,187 →
Application:
09/551,524 →
Trench Isolation Method for Semiconductor Integrated Circuit
Patent:
6,268,265 →
Application:
09/346,450 →
Planarization Method of Insulating Layer for Semiconductor Device
Patent:
6,423,639 →
Application:
09/603,202 →
Metallization Process for Manufacturing Semiconductor Devices
Patent:
6,335,284 →
Application:
09/386,360 →
Method for Fabricating a Semiconductor Memory Device and the Structure Thereof
Patent:
6,337,267 →
Application:
09/347,821 →
Method of fabricating floating gates in semiconductor device
Patent:
6,342,451 →
Application:
09/558,683 →
Method of Manufacturing a Capacitor Having Oxide Layers with Different Impurities and Method of Fabricating a Semiconductor Device Comprising the Same
Patent:
6,376,303 →
Application:
09/499,295 →
Method of Forming T-Shaped Isolation Layer, Method of Forming Elevated Salicide Source/Drain Region Using the Same, and Semiconductor Device Having T-Shaped Isolation Layer
Method of Forming T-Shaped Isolation Layer, Method of Forming Elevated Salicide Source/Drain Region Using the Same, and Semiconductor Device Having T-Shaped Isolation Layer
Patent:
6,383,877 →
Application:
09/573,268 →
Method for Fabricating a Capacitor of a Semiconductor Device and a Capacitor Made Thereby
Method for Fabricating a Capacitor of a Semiconductor Device and a Capacitor Made Thereby
Patent:
6,391,736 →
Application:
09/704,763 →
Non-Volatile Semiconductor Memory Device Capable of Reducing Read Time
Patent:
6,434,042 →
Application:
09/703,393 →
Nonvolatile Memory Devices Having Alternative Programming
Patent:
6,434,052 →
Application:
09/222,044 →
Trench Isolation Method for Semiconductor Integrated Circuit
Patent:
6,436,611 →
Application:
09/611,799 →
Semiconductor Memory Device Having a Plurality of Laser Fuses
Patent:
6,448,626 →
Application:
09/672,924 →
Semiconductor Memory Device with Redundancy Logic Cell and Repair Method
Methods of Forming Self-Aligned Contact Pads on Electrically Conductive Lines
Methods of Forming Self-Aligned Contact Pads on Electrically Conductive Lines
Patent:
6,268,252 →
Application:
09/442,523 →
Non-Volatile Semiconductor Memory Device
Method of Repairing a Failed Wordline
Non-Volatile Semiconductor Memory Device
Patent:
6,466,478 →
Application:
09/847,115 →
Bit Line Sensing Control Circuit for a Semiconductor Memory Device and Layout of the Same
Method of Forming Interlevel Dielectric Layer of Semiconductor Device
Nonvolatile Semiconductor Memory Device and Manufacturing Method Thereof
Nonvolatile Semiconductor Memory Device and Manufacturing Method Thereof
Level-Shifting Reference Voltage Source Circuits and Methods
Semiconductor Memory Device Having a Memory Block with a Decreased Capacitance
Semiconductor Device Having Trench Isolation Structure and Method of Forming Same
Semiconductor Device Having Trench Isolation Structure and Method of Forming Same
Wafer Polishing Slurry and Chemical Mechanical Polishing (Cmp) Method Using the Same
Reference Voltage Generator
Method for Depositing a Tungsten Silicide Layer
Pattern Formation Method Using Two Alternating Phase Shift Masks
Method of Forming Semiconductor Device Having a Gaa Type Transistor
Nonvolatile Semiconductor Memory Device Having Changeable Spare Memory Address
Memory System Capable of Increasing Utilization Efficiency of Semiconductor Memory Device and Method of Refreshing the Semiconductor Memory Device
Pecvd Method of Forming a Tungsten Silicide Layer on a Polysilicon Layer
Transfer Circuit of Semiconductor Device and Structure Thereof
Capacitor of an Integrated Circuit Device and Method of Manufacturing the Same
Capacitor of an Integrated Circuit Device and Method of Manufacturing the Same
Capacitor of an Integrated Circuit Device and Method of Manufacturing the Same
Capacitor of an Integrated Circuit Device and Method of Manufacturing the Same
Wiring Structure of Semiconductor Device
Wiring Structure of Semiconductor Device and Method for Manufacturing the Same
Patent:
6,355,515 →
Application:
09/359,243 →
Redundancy Circuit in Semiconductor Memory Device Having a Multiblock Structure
Delay Stage Insensitive to Operating Voltage and Delay Circuit Including the Same
Fixed Offset Digital-to-Analog Conversion Device and Method
Nonvolatile Semiconductor Memory Device with Scalable Two Transistor Memory Cells
Duty Cycle Correction Circuit of Delay Locked Loop and Delay Locked Loop Having the Duty Cycle Correction Circuit
Duty Cycle Correction Circuit of Delay Locked Loop and Delay Locked Loop Having the Duty Cycle Correction Circuit
Input Signal Receiving Device of Semiconductor Memory Unit
Semiconductor Memory Device with Cylindrical Storage Electrode and Method of Manufacturing the Same
Etching Method in a Semiconductor Processing and Etching System for Performing the Same
Etching Method in a Semiconductor Processing and Etching System for Performing the Same
Multi-Level High Voltage Generator
Flash Memory Device Capable of Preventing Program Disturbance According to Partial Programming
Non-Volatile Semiconductor Memory Device Having Shared Row Selection Circuit
Semiconductor Devices Having a Pocket Line and Methods of Fabricating the Same
Semiconductor Devices Having a Pocket Line and Methods of Fabricating the Same
Packet Addressing Programmable Dual Port Memory Devices and Related Methods
Duty Cycle Correction Circuit for Use in a Semiconductor Device
Differential Type Delay Cells and Methods of Operating the Same
High Voltage Generator Circuit with Ripple Stabilization Function
Cleaning Solution and Cleaning Method of a Semiconductor Device
Cleaning Solution and Cleaning Method of a Semiconductor Device
Cleaning Solution and Cleaning Method of a Semiconductor Device
Method of Forming a Metal Oxide Film
Method of Forming a Metal Oxide Film
Method of Forming an Interconnection Line in a Semiconductor Device
Etching Solution for Silicon Oxide and Method of Manufacturing a Semiconductor Device Using the Same
Nonvolatile Memory Device Having an Improved Integration and Reduced Contact Failure
Patent:
5,834,807 →
Application:
08/615,064 →
Sense Amplifier Circuit for Use in a Semiconductor Memory Device
Interface Circuit for Using in High-Speed Semiconductor Device and Interfacing Method
Reference Voltage Generator Tolerant to Temperature Variations
Tungsten layer formation method for semiconductor device and semiconductor device using the same
Patent:
6,404,054 →
Application:
09/609,927 →
Tungsten Layer Formation Method for Semiconductor Device and Semiconductor Device Using the Same
Patent:
6,579,794 →
Application:
09/357,126 →
Non-Volatile Semiconductor Memory Device Having Sense Amplifier with Increased Speed
Circuit and Method for Generating Wordline Voltage in Nonvolatile Semiconductor Memory Device
Trench Isolation Method with an Epitaxially Grown Capping Layer
Trench Isolation Method
Patent:
6,255,194 →
Application:
09/324,919 →
Semiconductor Devices Having a Contact Plug and Fabrication Methods Thereof
Methods of Forming Iintegrated Circuit Devices Having a Metal-Insulator-Metal (Mim) Capacitor
Data Driving Circuit and Semiconductor Memory Device Having the Same
Hierarchical Data Storage Management
Patent:
6,330,572 →
Application:
09/354,280 →
Data Transmission Installation of the Radio Network Type, and Corresponding Method
Patent:
5,689,510 →
Application:
08/307,579 →
System for Transmitting Messages to Improved Stations, and Corresponding Processing
Patent:
6,697,379 →
Application:
09/312,486 →
Method and Apparatus for Connecting Network Segments
Patent:
6,483,852 →
Application:
09/210,456 →
Method and Apparatus for Optimizing Performance and Battery Life of Electronic Devices Based on System and Application Parameters
Patent:
7,111,179 →
Application:
10/268,914 →
Method and System for State-Dependent Admission Control and Routing of Multi-Rate Circuit-Switched Traffic
Patent:
6,366,559 →
Application:
09/092,732 →
Adaptive Layered Coding for Voice Over Wireless Ip Applications
Patent:
6,434,191 →
Application:
09/653,913 →
Measurement of Packet Loss Ratio in a Network Using End-Point Data
Method and Systems for Bandwidth Management in Packet Data Networks
Method and System for Design and Routing in Transparent Optical Networks
Dynamic Traffic Rearrangement and Restoration for Mpls Networks with Differentiated Services Capabilities
Dynamic Traffic Rearrangement and Restoration for Mpls Networks with Differentiated Services Capabilities
Self-Locating Remote Monitoring Systems
Patent:
5,650,770 →
Application:
08/547,026 →
Voice-Activated Personal Alarm
Self-Locating Remote Monitoring Systems
Patent:
6,198,390 →
Application:
09/325,030 →
Multi-Hazard Alarm System Using Selectable Power-Level Transmission and Localization
Self-Locating Remote Monitoring Systems
Patent:
5,963,130 →
Application:
08/849,998 →
Multi-Hazard Alarm System Using Selectable Power-Level Transmission and Localization
Patent:
5,461,365 →
Application:
08/330,901 →
Demonstration Control Adjunct Device for Printers
Demonstration Control Adjunct Device for Printers
Patent:
6,747,752 →
Application:
09/187,267 →
Semiconductor Memory Arrays
Patent:
5,737,271 →
Application:
08/808,205 →
Delay Locking High Speed Clock Synchronization Method And Circuit
Patent:
6,310,822 →
Application:
09/498,739 →
Internal Power Management Scheme for a Memory Chip in Deep Power Down Mode
Internal Power Management Scheme for a Memory Chip in Deep Power Down Mode
Non-Volatile Memory Devices and Control and Operation Thereof
Non-Volatile Memory Devices and Control and Operation Thereof
Non-Volatile Memory Devices and Control and Operation Thereof
Contiguous Block Addressing Scheme
Contiguous Block Addressing Scheme
Contiguous Block Addressing Scheme
Contiguous Block Addressing Scheme
Semiconductor Memory Having Segmented Row Repair
Semiconductor memory having segmented row repair
Patent:
6,314,030 →
Application:
09/594,442 →
Circuit, System and Method for Selectively Turning Off Internal Clock Drivers
Circuit, System and Method for Selectively Turning Off Internal Clock Drivers
Circuit, System and Method for Selectively Turning Off Internal Clock Drivers
Method of Making a Field Effect Transistor Having an Elevated Source and an Elevated Drain
Patent:
6,057,200 →
Application:
08/831,360 →
Field Effect Transistor Comprising Electrically Conductive Plugs Having Monocrystalline and Polycrystalline Silicon
Patent:
5,831,334 →
Application:
08/912,899 →
Semiconductor Constructuions Comprising Electrically Conductive Plugs Having Monocrystalline and Polycrystalline Silicon
Patent:
5,998,844 →
Application:
09/153,088 →
A Field Effect Transistor
Patent:
5,677,573 →
Application:
08/743,502 →
Method of Making a Field Effect Transistor Having an Elevated Source and an Elevated Drain
Patent:
5,637,518 →
Application:
08/543,705 →
Erase Block Architecture for Non-Volatile Memory
Erase Block Architecture for Non-Volatile Memory
Patent:
6,587,383 →
Application:
10/100,856 →
Synchronous Dram with Selectable Internal Prefetch Size
Synchronous Dram with Selectable Internal Prefetch Size
Synchronous Dram with Selectable Internal Prefetch Size
Memory Device with Distributed Voltage Regulation System
Patent:
5,818,780 →
Application:
08/717,170 →
Memory Device with Distributed Voltage Regulation System
Patent:
6,009,034 →
Application:
09/167,042 →
Memory Device with Distributed Voltage Regulation System
Patent:
6,307,802 →
Application:
09/454,532 →
Memory Device with Distributed Voltage Regulation System
Patent:
5,574,697 →
Application:
08/515,485 →
Method for an Erase Operation of Flash Memory Using a Source Regulation Circuit
Patent:
6,222,770 →
Application:
09/251,035 →
Source Regulation Circuit for Flash Memory
Source Regulation Circuit for an Erase Operation of Flash Memory
Patent:
6,097,632 →
Application:
08/844,191 →
Delay-Locked Loop with Binary-Coupled Capacitor
Delay-Locked Loop with Binary-Coupled Capacitor
Delay-Locked Loop with Binary-Coupled Capacitor
Delay-Locked Loop with Binary-Coupled Capacitor
Patent:
6,400,641 →
Application:
09/353,571 →
Delay-locked loop with binary-coupled capacitor
Patent:
6,262,921 →
Application:
09/570,241 →
Delay-locked loop with binary-coupled capacitor
Patent:
6,256,259 →
Application:
09/570,242 →
Delay-Locked Loop with Binary-Coupled Capacitor
Patent:
5,946,244 →
Application:
08/811,918 →
Device and Method for Repairing a Semiconductor Memory
Device and Method for Repairing a Semiconductor Memory
Method for Repairing a Semiconductor Memory
Method for Repairing a Semiconductor Memory
Memory Device and Method for Repairing a Semiconductor Memory
Memory Device and Method for Repairing a Semiconductor Memory
Memory Device and Method for Repairing a Semiconductor Memory
Device and Method for Repairing a Semiconductor Memory
Patent:
6,199,177 →
Application:
09/143,283 →
Memory Cell Arrays Comprising Intersecting Slanted Portions
Patent:
6,410,948 →
Application:
09/340,983 →
Memory Cell Arrays
Method of Making Memory Cell Arrays
Patent:
6,607,944 →
Application:
09/918,345 →
Metal Local Interconnect Self-Aligned Source Flash Cell
Data Path Having Grounded Precharge Operation and Test Compression Capability
Data Path Having Grounded Precharge Operation and Test Compression Capability
Flash Memory Device with Improved Programming Performance
Flash Memory Device with Improved Programming Performance
Flash Memory Device with Improved Programming Performance
Method for Forming Texturized Polysilicon
Patent:
5,913,128 →
Application:
08/959,648 →
Circuit for Canceling and Replacing Redundant Elements
Patent:
5,838,620 →
Application:
08/796,148 →
Circuit for Cancelling and Replacing Redundant Elements
Patent:
5,677,884 →
Application:
08/816,203 →
Circuit for Cancelling and Replacing Redundant Elements
Patent:
6,208,568 →
Application:
09/133,714 →
Circuit for Cancelling and Replacing Redundant Elements
Patent:
5,912,579 →
Application:
09/133,586 →
Input/Output Device Having Shared Active Area
Patent:
5,978,287 →
Application:
08/781,490 →
Capacitor Structures
Method of Forming Dram Trench Capacitor with Metal Layer Over Hemispherical Grain Polysilicon
Method for Detecting or Repairing Intercell Defects in More Than One Array of a Memory Device
Patent:
6,510,533 →
Application:
09/749,854 →
Method for Detecting or Repairing Intercell Defects in More Than One Array of a Memory Device
Patent:
6,167,541 →
Application:
09/047,760 →
Circuits and methods for selectively coupling redundant elements into an integrated circuit
Patent:
6,333,887 →
Application:
09/596,966 →
Circuits and Methods for Selectively Coupling Redundant Elements into an Integrated Circuit
Patent:
6,077,211 →
Application:
09/031,868 →
Apparatus and Method for Increasing Test Flexibility of a Memory Device
Patent:
6,459,635 →
Application:
09/703,360 →
Apparatus and Method for Increasing Test Flexibility of a Memory Device
Patent:
6,141,276 →
Application:
09/389,680 →
Hierarchical Memory Array Structure with Redundant Components Having Electrically Isolated Bit Lines
Patent:
5,734,620 →
Application:
08/661,810 →
Hierarchical Memory Array Structure Having Electrically Isolated Bit Lines for Temporary Data Storage
Patent:
5,724,301 →
Application:
08/752,578 →
Hierarchical Memory Array Structure Having Electrically Isolated Bit Lines for Temporary Data Storage
Patent:
5,600,602 →
Application:
08/417,213 →
Reduced Area Sense Amplifier Isolation Layout in a Dynamic Ram Architecture
Reduced Area Sense Amplifier Isolation Layout in a Dynamic Ram Architecture
Reduced Area Sense Amplifier Isolation Layout in a Dynamic Ram Architecture
Patent:
6,480,407 →
Application:
08/519,504 →
Integrated Circuitry Fuse Forming Methods, Integrated Circuitry Programming Methods, and Related Integrated Circuitry
Patent:
6,300,170 →
Application:
09/393,548 →
Integrated circuitry fuse forming methods, integrated circuitry programming methods, and related integrated circuitry
Patent:
6,265,299 →
Application:
09/556,245 →
Integrated Circuitry Fuse Forming Methods, Integrated Circuitry Programming Methods, and Related Integrated Circuitry
Integrated Circuitry Fuse Forming Methods, Integrated Circuitry Programming Methods, and Related Integrated Circuitry
Patent:
6,238,955 →
Application:
09/135,377 →
Integrated Circuitry Fuse Forming Methods, Integrated Circuitry Programming Methods, and Related Integrated Circuitry
Patent:
6,249,037 →
Application:
09/135,392 →
Integrated Circuitry Fuse Forming Methods, Integrated Circuitry Programming Methods, and Related Integrated Circuitry
Patent:
5,976,917 →
Application:
09/015,414 →
Capacitor Constructions
Methods of Forming Capacitors
Method of Anti-Fuse Repair
Patent:
5,978,248 →
Application:
09/030,130 →
Method of anti-fuse repair
Patent:
6,233,194 →
Application:
09/560,498 →
Method of Anti-Fuse Repair
Antifuse Structure and Method of Use
Method of Anti-Fuse Repair
Patent:
5,742,555 →
Application:
08/700,234 →
Antifuse Structure and Method of Use
Patent:
6,836,000 →
Application:
09/515,760 →
Graded Layer for Use in Semiconductor Circuits and Method for Making Same
Graded Layer for Use in Semiconductor Circuits and Method for Making Same
Graded Layer for Use in Semiconductor Circuits and Method for Making Same
Patent:
6,271,590 →
Application:
09/138,811 →
Methods and Apparatus for Duty Cycle Control
Circuit and Method for Testing a Memory Device with a Cell Plate Generator Having a Variable Current
Patent:
5,943,276 →
Application:
09/031,973 →
Voltage Generator with First Drive Current in Test Mode and Second Drive Current in Normal Operation
Patent:
6,134,162 →
Application:
09/360,952 →
Circuit and method for testing a memory device
Patent:
6,327,200 →
Application:
09/640,610 →
Circuit and method for testing a memory device
Patent:
6,359,817 →
Application:
09/640,611 →
Circuit and Method for Testing a Memory Device
Circuit and Method for Testing a Memory Device with a Cell Plate Generator Having a Variable Current
Patent:
5,822,258 →
Application:
08/851,416 →
Method of Making a Concave Capacitor
Patent:
6,682,984 →
Application:
09/535,483 →
Capacitor Structure
Patent:
6,459,116 →
Application:
09/283,606 →
Capacitor Structure
Capacitor Structure
Capacitor Structure
Method of Making a Capacitor
Patent:
6,043,119 →
Application:
08/906,213 →
Sequential Pulse Deposition
Sequential Pulse Deposition
System for Testing Integrated Circuit Devices
System for Testing Integrated Circuit Devices
Sysrem for Testing Integrated Circuit Devices
Patent:
6,496,027 →
Application:
08/916,994 →
Semiconductor Circuit Design Methods, Semiconductor Processing Methods and Integrated Circuitry
A Semiconductor Circuit Design Method for Employing Spacing Constraints and Circuits Thereof
Patent:
6,223,331 →
Application:
09/126,877 →
Method for Reducing Gaseous Species of Contamination in Wet Processes
Patent:
6,521,049 →
Application:
09/327,152 →
Device Addressing Gas Contamination in a Wet Process
Method for Reducing Gaseous Species of Contamination in Wet Processes
Patent:
6,001,189 →
Application:
08/724,578 →
Method of Forming a Capacitor
Method of Forming a Capacitor and a Capacitor Construction
Capacitor Constructions
Patent:
6,900,496 →
Application:
08/886,388 →
Method of Forming a Capacitor and a Capacitor Construction
Patent:
6,214,687 →
Application:
09/251,387 →
Method of Forming a Capacitor
Patent:
6,218,237 →
Application:
08/582,385 →
Laser Selection of Ions for Sputter Deposition of Titanium Containing Films
Patent:
6,752,912 →
Application:
09/384,740 →
Method and Apparatus for Depositing Films
Enhanced Collimated Deposition
Patent:
6,827,824 →
Application:
08/631,465 →
Chemical Vapor Deposition of Titanium from Titanium Tetrachloride and Hydrocarbon Reactants
Patent:
6,184,136 →
Application:
09/292,993 →
Chemical vapor deposition of titanium from titanium tetrachloride and hydrocarbon reactants
Chemical Vapor Deposition of Titanium from Titanium Tetrachloride and Hydrocarbon Reactants
Chemical Vapor Deposition of Titanium from Titanium Tetrachloride and Hydrocarbon Reactants
Chemical Vapor Deposition of Titanium from Titanium Tetrachloride and Hydrocarbon Reactants
Chemical Vapor Deposition of Titanium from Titanium Tetrachloride and Hydrocarbon Reactants
Patent:
5,946,594 →
Application:
08/581,765 →
Collimated Sputter Deposition Monitor Using Sheet Resistance
Collimated Sputter Deposition Monitor Using Sheet Resistance
Patent:
6,436,246 →
Application:
08/788,980 →
Method of Making Cup-Shaped Dram Capacitor Having an Inwardly Overhang Ing Lip
Patent:
5,518,948 →
Application:
08/534,572 →
Method of Producing an Etch Pattern
Patent:
6,420,270 →
Application:
09/645,906 →
Cell Capacitors, Memory Cells, Memory Arrays, and Method of Fabrication
Patent:
6,429,475 →
Application:
09/645,251 →
Cell Capacitors, Memory Cells, Memory Arrays, and Method of Fabrication
Patent:
6,153,903 →
Application:
09/204,526 →
Cell Capacitors, Memory Cells, Memory Arrays, and Method of Fabrication
Patent:
6,225,159 →
Application:
09/426,965 →
Cell Capacitors, Memory Cells, Memory Arrays, and Method of Fabrication
Patent:
6,063,656 →
Application:
08/844,512 →
Electrostatic Method and Apparatus for Vaporizing Precursors and System for Using Same
Patent:
6,280,793 →
Application:
08/752,834 →
Multiplication of Storage Capacitance in Memory Cells by Using the Miller Effect
Patent:
5,835,403 →
Application:
08/879,908 →
Multiplication of Storage Capacitance in Memory Cells by Using the Miller Effect
Patent:
5,995,410 →
Application:
09/123,634 →
Multiplication of Storage Capacitance in Memory Cells by Using the Miller Effect
Patent:
5,666,306 →
Application:
08/706,662 →
Solvent Prewet and Method to Dispense the Solvent Prewet
Patent:
6,147,010 →
Application:
08/974,015 →
Solvent prewet and method and apparatus to dispense the solvent prewet
Patent:
6,284,676 →
Application:
09/650,876 →
Solvent Prewet and Method to Dispense the Solvent Prewet
Solvent Prewet and Method and Apparatus to Dispense the Solvent Prewet
Solvent Prewet and Method and Apparatus to Dispense the Solvent Prewet
Method and Apparatus for Controlling Rate of Pressure Change in a Vacuum Process Chamber
Dilute Cleaning Composition and Method for Using Same
Patent:
6,313,048 →
Application:
09/325,375 →
Dilute Composition Cleaning Method
Patent:
6,136,767 →
Application:
09/196,661 →
Dilute Cleaning Composition and Method for Using Same
Dilute Cleaning Composition and Method for Using Same
Dilute Cleaning Composition
Surface cleaning apparatus
Patent:
6,269,511 →
Application:
09/679,806 →
Surface Cleaning Apparatus and Method
Patent:
6,273,100 →
Application:
09/141,384 →
Polysilicon-Silicon Dioxide Cleaning Process Performed in an Integrated Cleaner with Scrubber
Patent:
6,358,325 →
Application:
09/468,022 →
Methods of Forming Field Effect Transistors
Methods of Forming Field Effect Transistors and Related Field Effect Transistor Constructions
Methods of Forming Field Effect Transistors and Related Field Effect Transistor Constructions
Methods of Forming Field Effect Transistors and Related Field Effect Transistor Constructions
Methods of Forming Field Effect Transistors and Related Field Effect Transistor Constructions
Patent:
6,400,002 →
Application:
09/490,257 →
Methods of forming field effect transistors and related field effect transistor constructions
Patent:
6,344,382 →
Application:
09/494,835 →
Methods of Forming Field Effect Transistors and Related Field Effect Transistor Constructions
Methods of Forming Field Effect Transistors and Related Field Effect Transistor Constructions
Patent:
6,406,957 →
Application:
09/494,973 →
Methods of forming field effect transistors and related field effect transistor constructions
Methods of forming field effect transistors and related field effect transistor constructions
Patent:
6,335,246 →
Application:
09/494,836 →
Methods of Forming Field Effect Transistors and Related Field Effect Transistor Constructions
Patent:
6,025,232 →
Application:
08/968,085 →
Rhodium-Rich Integrated Circuit Capacitor Electrode
Integrated Circuits with Rhodium-Rich Structures
Methods to Form Rhodium-Rich Oxygen Barriers
Rhodium-Rich Oxygen Barriers
Method and Apparatus for Inspecting Wafers
Selective Method to Form Roughened Silicon
Selective Method to Form Roughened Silicon
Patent:
6,355,536 →
Application:
09/093,217 →
Polishing Systems, Methods of Polishing Substrates, and Methods of Cleaning Polishing Slurry from Substrate Surfaces
Polishing Systems, Methods of Polishing Substrates, and Methods of Preparing Liquids for Semiconductor Fabrication Processes
Patent:
6,716,802 →
Application:
09/298,160 →
Polishing Systems, Methods of Polishing Substrates, and Methods of Preparing Liquids for Semiconductor Fabrication Processes
Patent:
6,206,757 →
Application:
09/298,012 →
Polishing Systems, Methods of Polishing Substrates, and Methods of Preparing Liquids for Semiconductor Fabrication Processes
Patent:
6,200,196 →
Application:
09/298,312 →
Polishing Systems Methods of Polishing Substrates and Method of Preaparing Liquids for Semiconductor Fabrication Process.
Patent:
6,007,406 →
Application:
08/984,730 →
Boride Electrodes and Barriers for Cell Dielectrics
Patent:
6,316,800 →
Application:
09/563,909 →
Boride Electrodes and Barriers for Cell Dielectrics
Boride Electrodes and Barriers for Cell Dielectrics
Patent:
6,111,285 →
Application:
09/042,791 →
Barrier-Metal-Free Copper Damascene Technology Using Atomic Hydrogen Enhanced Reflow
Barrier-Metal-Free Copper Damascene Technology Using Atomic Hydrogen Enhanced Reflow
Barrier-Metal-Free Copper Camascence Technology Using Atomic Hydrogen Enhanced Reflow
Barrier-Metal-Free Copper Damascene Technology Using Enhanced Reflow
Barrier-Metal-Free Copper Damascene Technology Using Atomic Hydrogen Enhanced Reflow
Barrier-Metal-Free Copper Damascene Technology Using Atomic Hydrogen Enhanced Reflow
Barrier-Metal-Free Copper Damascene Technology Using Atomic Hydrogen Enhanced Reflow
Methods for Forming and Integrated Circuit Structures Containing Ruthenium and Tungsten Containing Layers
Methods for Forming and Integrated Circuit Structures Containing Ruthenium and Tungsten Containing Layers
Methods for Forming and Integrated Circuit Structures Containing Ruthenium and Tungsten Containing Layers
Patent:
7,253,076 →
Application:
09/590,795 →
Dynamic Memory Based on Single Electron Storage
Dynamic Memory Based on Single Electron Storage
Method for Forming Raised Structures by Controlled Selective Epitaxial Growth of Facet Using Spacer
Diffusion Barrier Layers and Methods of Forming Same
Patent:
6,323,081 →
Application:
09/146,866 →
Carburized Silicon Gate Insulators for Integrated Circuits
Patent:
6,794,255 →
Application:
09/258,467 →
Carburized Silicon Gate Insulators for Integrated Circuits
Patent:
6,731,531 →
Application:
09/650,553 →
Reticle Cleaning Without Damaging Pellicle
Patent:
6,063,208 →
Application:
09/310,520 →
Reticle Cleaning Without Damaging Pellicle
Patent:
6,458,216 →
Application:
09/543,036 →
Reticle cleaning without damaging pellicle
Patent:
6,284,417 →
Application:
09/651,392 →
Reticle Cleaning Without Damaging Pellicle
Reticle Cleaning Without Damaging Pellicle
Reticle Cleaning Without Damaging Pellicle
Reticle Cleaning Without Damaging Pellicle
Reticle Cleaning Without Damaging Pellicle
Patent:
6,165,650 →
Application:
09/310,521 →
Reticle Cleaning Without Damaging Pellicle
Patent:
5,938,860 →
Application:
08/921,656 →
Thermal Processing of Metal Alloys for an Improved Cmp Process in Integrated Circuit Fabricatin
Thermal Processing of Metal Alloys for an Improved Cmp Process in Integrated Circuit Fabrication
Thermal Processing of Metal Alloys for an Improved Cmp Process in Integrated Circuit Fabrication
Patent:
6,316,356 →
Application:
09/038,252 →
Methods and Solutions for Cleaning Polished Aluminum-Containing Layers, Methods for Making Metallization Structures, and the Structures Resulting from These Methods
Methods and Solutions for Cleaning Polished Aluminum-Containing Layers, Methods for Making Metallization Structures, and the Structures Resulting from These Methods
Patent:
6,265,781 →
Application:
09/153,053 →
Enhanced Capacitor Shape
Patent:
6,391,709 →
Application:
09/394,401 →
Enhanced Capacitor Shape
Enhanced Capacitor Shape
Patent:
6,369,432 →
Application:
09/028,050 →
Semiconductor Constructions Comprising Aluminum-Containing Layers
Patent:
6,278,188 →
Application:
09/107,929 →
Semiconductor Constructions Compromising Aluminum-Containing Layers
Semiconductor Processing Methods of Polishing Aluminum-Comprising Layers
Patent:
6,339,026 →
Application:
09/066,614 →
Double Layer Electrode and Barrier System on Hemispherical Grain Silicon for Use with High Dielectric Constant Materials and Methods for Fabricating the Same
Double Layer Electrode and Barrier System on Hemispherical Grain Silicon for Use with High Dielectric Constant Materials and Methods for Fabricating the Same
Double Layer Electrode and Barrier System on Hemispherical Grain Silicon for Use with High Dielectric Constant Materials and Methods for Fabricating the Same
Patent:
6,281,543 →
Application:
09/386,833 →
Gapped-Plate Capacitor
Patent:
6,498,363 →
Application:
09/652,837 →
Gapped-Plate Capacitor
Gapped-Plate Capacitor
Gapped-Plate Capacitor
Gapped-Plate Capacitor
Patent:
6,316,326 →
Application:
09/229,857 →
Gapped-Plate Capacitor
Patent:
6,018,175 →
Application:
09/148,032 →
Aluminum-Beryllium Alloys for Air Bridges
Aluminum-Beryllium Alloys for Air Bridges
Aluminum-Beryllium Alloys for Air Bridges
Patent:
6,509,590 →
Application:
09/119,355 →
Deadhesion Method and Mechanism for Wafer Processing
Deadhesion Method and Mechanism for Wafer Processing
Deadhesion Method and Mechanism for Wafer Processing
Patent:
6,316,363 →
Application:
09/387,429 →
Chemical Treatment of Semiconductor Substrates
Chemical Treatment of Semiconductor Substrates
Chemical Treatment of Semiconductor Substrates
Chemical Treatment of Semiconductor Substrates
Patent:
6,395,647 →
Application:
09/388,570 →
Capacitor Electrode for Integrating High K Materials
Capacitor Electrode for Integrating High K Materials
Patent:
6,750,500 →
Application:
09/225,887 →
Methods of Forming Semiconductor Circuit Constructions and Capacitor Constructions
Semiconductor Circuit Constructions, Capacitor Constructions, and Methods of Forming Semiconductor Circuit Constructions and Capacitor Constructions
Patent:
6,555,863 →
Application:
09/566,673 →
Semiconductor Circuit Constructions,Capacitor Constructions, and Methods of Forming Semiconductor Circuit Constructions and Capacitor Constructions
Methods of Forming Semiconductor Circuit Constructions and Capacitor Constructions
Methods of Forming Materials Comprising Tungsten and Nitrogen
Methods of Forming Materials Comprising Tungsten and Nitrogen, and Methods of Forming Capacitors
Methods of Forming Materials Comprising Tungsten and Nitrogen
Isolation and/or Removal of Ionic Contaminants from Planarization Fluid Compositions Using Macrocyclic Polyethers
Patent:
6,458,290 →
Application:
09/642,682 →
Isolation and/or Removal of Ionic Contaminants from Planarization Fluid Compositions Using Macrocyclic Polyethers and Methods of Using Such Compositions
Patent:
6,468,909 →
Application:
09/146,299 →
Shared Length Cell for Improved Capacitance
Shared Length Cell for Improved Capacitance
Patent:
6,180,452 →
Application:
09/436,213 →
Shared Length Cell for Improved Capacitance
Patent:
6,025,624 →
Application:
09/099,765 →
Continuous Good Step Coverage Cvd Platinum Metal Deposition
Continuous Good Step Coverage Cvd Platinum Metal Deposition
Patent:
6,750,110 →
Application:
09/121,528 →
System and Method for Selectively Increasing Surface Temperature of an Object
System and Method for Selectively Increasing Surface Temperature of an Object
Organic Field Ionization Source
Organic Field Ionization Source
Patent:
6,265,722 →
Application:
09/386,976 →
Reduction of Surface Roughness During Chemical Mechanical Planarization(Cmp)
Patent:
6,426,295 →
Application:
09/584,468 →
Reduction of Surface Roughness During Chemical Mechanical Planarization (Cmp)
Composition and Method of Formation and Use Therefor in Chemical-Mechanical Polishing
Composition and Method of Formation and Use Therefor in Chemical-Mechanical Polishing
Patent:
6,409,936 →
Application:
09/252,022 →
Methods of Forming Capacitors and Resultant Capacitor Structures
Integrated Circuit Capacitor Structures
Methods of Forming Capacitors and Resultant Capacitor Structures
Methods of Forming Capacitors and Resultant Capacitor Structures
Patent:
6,403,442 →
Application:
09/389,533 →
Integrated Circuitry
Method of Forming Integrated Circuitry, and Method of Forming a Contact Opening
Solutions of Metal-Comprising Materials, Methods of Forming Metal-Comprising Layers, Methods of Storing Metal-Comprising Materials, and Methods of Forming Capacitors
Solutions of Metal-Comprising Materials, and Methods of Making Solutions of Metal-Comprising Materials
Solutions of Metal-Comprising Materials
Methods of Making Semiconductor Devices
Patent:
6,319,832 →
Application:
09/253,307 →
Method of Forming High Aspect Ratio Structures for Seminconductor Devices
Patent:
6,204,143 →
Application:
09/293,635 →
Method for Improved Processing and Etchback of a Container Capacitor
Method for Improved Processing and Etchback of a Container Capacitor
Method for Improved Processing and Etchback of a Container Capacitor
Patent:
6,319,789 →
Application:
09/235,752 →
Method of Depositing a Nitrogen Enriched Metal Layer, Method of Forming a Silicide Contact to a Silicon Comprising Substrate, Method of Forming a Metal Source Layer in an Integrated Circuit, Method of Analyzing Impact of Operating Parameter Changes for a Plasma Depositio
Patent:
6,365,507 →
Application:
09/260,237 →
Low Dielectric Silicon Oxynitride Spacer Films and Devices Incorporating Such Films
Method of Forming Low Dielectric Silicon Oxynitride Spacer Films Highly Selective to Etchants
Method of Forming Low Dielectric Silicon Oxynitride Spacer Films Highly Selective to Etchants
Patent:
6,518,626 →
Application:
09/507,463 →
Capacitor and method of forming a capacitor
Patent:
6,313,496 →
Application:
09/654,930 →
Method of Forming a Capacitor
Methods for Enhancing Capacitors in Integrated Circuits
Structures and Methods for Enhancing Capacitors in Integrated Circuits
Structures and Methods for Enhancing Capacitors in Integrated Circuits
Patent:
7,009,240 →
Application:
09/598,355 →
An Apparatus for the in Situ Alignment of a Mask and a Semiconductor Wafer.
Apparatus and Method for Feature Edge Detection in Semiconductor Processing
Apparatus and Method for Feature Edge Detection in Semiconductor Processing
Patent:
6,624,897 →
Application:
09/292,396 →
Methods of Forming Nitrogen-Containing Masses, Silicon Nitride Layers, and Capacitor Constructions
Semiconductor Constructions
Methods of Forming Semiconductor Constructions
Methods of Forming Nitrogen-Containing Masses, Silicon Nitride Layers, and Capacitor Constructions
Integrated Circuitry and Dram Circuitry
Patent:
6,570,204 →
Application:
09/654,297 →
Method of Forming a Pair of Capacitors Having a Common Capacitor Electrode, Method of Forming Dram Circuitry, Integrated Circuitry and Dram Circuitry
Patent:
6,277,687 →
Application:
09/323,440 →
Method of Forming Flow-Fill Structures
Flow-Fill Spacer Structures for Flat Panel Display Device
Flow-Fill Structures
Flow-Fill Spacer Structures for Flat Panel Display Device
A Method of Forming Flow-Fill Structures
Patent:
6,716,077 →
Application:
09/572,079 →
Delivery of Dissolved Ozone
Delivery of Dissolved Ozone
Patent:
6,758,938 →
Application:
09/386,247 →
Top Electrode in a Strongly Oxidizing Environment
Top Electrode in a Strongly Oxidizing Environment
Patent:
6,682,969 →
Application:
09/652,863 →
Stereolithographic Method and Apparatus for Packaging Electronic Components and Resulting Structures
Patent:
6,549,821 →
Application:
09/259,142 →
Energy Beam Patterning of Protective Layers for Semiconductor Devices
Patent:
6,544,902 →
Application:
09/652,340 →
Stereolithographic Method and Apparatus for Packaging Electronic Components
Stereolithographic Method for Applying Materials to Electronic Component Substrates and Resulting Structures
Patent:
6,524,346 →
Application:
09/259,143 →
Method for Producing Water for Use in Manufacturing Semiconductors
Method for Producing Water for Use in Manufacturing Semiconductors
Apparatus for Producing Water for Use in Manufacturing Semiconductors
Method for Producing Water for Use in Manufacturing Semiconductors
Patent:
6,440,382 →
Application:
09/387,119 →
Forming Sidewall Oxide Layers for Trench Isolation
Patent:
6,548,372 →
Application:
09/685,531 →
Methods for Stereolithographic Processing of Components and Assemblies
Apparatus for Stereolithographic Processing of Components and Assemblies
Low K Film Application for Interlevel Dielectric and Method of Cleaning Etched Features
Low K Film Application for Interlevel Dielectric and Method of Cleaning Etched Features
Dry Low K Film Application for Interlevel Dielectric and Method of Cleaning Etched Features
Patent:
6,573,175 →
Application:
09/998,729 →
Memory Structure with an Annealed Film
Method of Fabricating an SRRUO3 Film
Method of fabricating an SrRuO3 Film
Patent:
6,342,445 →
Application:
09/571,718 →
Method of Selective Oxidation in Semiconductor Manufacture
Patent:
6,458,714 →
Application:
09/721,839 →
Processes to Form a Metallic Film Stack
Platinum-Rhodium Stack as an Oxygen Barrier in an Integrated Circuit Capacitor
System for Depositing a Layered Film
Platinum-Rhodium Stack as an Oxygen Barrier
Semiconductor Processing Methods
Method for Removing Organic Material from a Substrate and for Oxidizing Oxidizable Material Thereon
Localized Array Threshold Voltage Implant Enhance Charge Storage Within Dram Memory Cells
Patent:
6,800,520 →
Application:
10/234,576 →
Localized Array Threshold Voltage Implant to Enhance Charge Storage Within Dram Memory Cells
Localized Array Threshold Voltage Implant to Enhance Charge Storage Within Dram Memory Cells
Detection Devices, Methods and Systems for Gas Phase Materials
Detection Devices, Methods and Systems for Gas Phase Materials
Sensor Devices, Methods and Systems for Detecting Gas Phase Materials
Patent:
6,479,297 →
Application:
09/652,634 →
Integrated Circuit Devices Having Contact and Container Structures
Methods for Forming Contact and Container Structures, and Integrated Circuit Devices Therefrom
Patent:
6,383,868 →
Application:
09/653,501 →
Needle Comb Reticle Pattern for Critical Dimension and Registration Measurements Using a Registration Tool and Methods for Using Same
Mixed Composition Interface Layer and Method of Forming
Mixed Composition Interface Layer and Method of Forming
Patent:
43,025 →
Application:
12/566,533 →
Dram Cell Constructions
Methods of Forming Dram Cells
Dram Cell Constructions
Dram Cell Constructions, and Methods of Forming Dram Cells
Patent:
6,429,070 →
Application:
09/651,484 →
Dram Constructions and Dram Devices
Method of Forming Drams, Methods of Forming Access Transistors for Dram Devices, and Methods of Forming Transistor Source/Drain Regions
Method of Forming a Capacitor Container Electrode and Method of Patterning a Metal Layer by Selectively Silicizing the Electrode or Metal Layer and Removing the Silicized Portion
Patent:
6,372,574 →
Application:
09/586,321 →
Reduced Aspect Ratio Digit Line Contact Process Flow Used During the Formation of a Semiconductor Device
Reduced Aspect Ratio Digit Line Contact Process Flow Used During the Formation of a Semiconductor Device
Integrated Decoupling Capacitors
Integrated Decoupling Capacitors
A Capacitor Having Rusixoy-Containing Adhesion Layers
Rusixoy-Containing Adhesion Layers
Method of Manufacturing a Capacitor Having Rusixoy-Containing Adhesion Layers
Process for Fabricating Rusixoy-Containing Adhesion Layers
Capacitor Having Rusixoy-Containing Adhesion Layers
Rusixoy-Containing Adhesion Layers
Process for Fabricating Rusixoy-Containing Adhesion Layers
Process for Fabricating Rusixoy-Containing Adhesion Layers
Process for Fabricating Rusixoy-Containing Adhesion Layers
Patent:
6,461,909 →
Application:
09/651,859 →
Cvd of Ptrh with Good Adhesion and Morphology
Method and Apparatus for Controlling Radiation Beam Intensity Directed to Microlithograhic Substrates
Method and Apparatus for Controlling Radiation Beam Intensity Directed to Microlithographic Substrates
Method for Controlling Radiation Beam Intensity Directed to Microlithographic Substrates
Nanotube Semiconductor Devices and Methods for Making the Same
Nanotube Semiconductor Devices and Methods for Making the Same
Nanotube Semiconductor Devices and Methods for Making the Same
Patent:
6,515,325 →
Application:
10/092,829 →
Microlithographic Mask Structures and Method of Fabrication
Microlithographic Device, Microlithographic Assist Features, System for Forming Contacts and Other Structures, and Method of Determining Mask Patterns
Reducing Asymmetrically Deposited Film Induced Registration Error
Reducing Asymmetrically Deposited Film Induced Registration Error
Reducing Asymmetrically Deposited Film Induced Registration Error
Reducing Asymmetrically Deposited Film Induced Registration Error
Apparatus and System for Removing Photoresist Through the Use of Hot Deionized Water Bath, Water Vapor and Ozone Gas
Removal of Photoresist Through the Use of Hot Deionized Water Bath, Water Vapor and Ozone Gas
Patent:
6,558,477 →
Application:
09/688,757 →
Pseudo Variable Resistor for Tester Platform
Method of Forming Memory Circuitry and Method of Forming Memory Circuitry Comprising a Buried Bit Line Array of Memory Cells
Patent:
6,376,380 →
Application:
09/652,601 →
Method and Apparatus for the Fabrication of Ferroelectric Films
Process for the Fabrication of Oxide Films
Method and Apparatus for the Fabrication of Ferroelectric Films
Dielectric Material Forming Methods and Enhanced Dielectric Materials
Dielectric Material Forming Methods and Enhanced Dielectric Materials
Solvated Ruthenium Precursors for Direct Liquid Injection of Ruthenium and Ruthenium Oxide and Method of Using Same
Patent:
6,541,067 →
Application:
09/506,962 →
Methods for preparing ruthenium oxide films
Patent:
6,281,125 →
Application:
09/573,034 →
Solvated Ruthenium Precursors for Direct Liquid Injection of Ruthenium and Ruthenium Oxide
Solvated Ruthenium Precursors for Direct Liquid Injection of Ruthenium and Ruthenium Oxide
Solvated Ruthenium Precursors for Direct Liquid Injection Ofruthenium and Ruthenium Oxide
Methods for Preparing Ruthenium Metal Films
Patent:
6,074,945 →
Application:
09/140,878 →
Methods for Preparing Ruthenium Oxide Films
Patent:
6,133,159 →
Application:
09/140,932 →
Network Architecture for Data Communication
Rear Drive Electric Vehicle
Patent:
5,562,178 →
Application:
08/438,111 →
Suppression of Multiple Noise-Related Signals in Pulse Width Modulated Signals
Patent:
5,637,971 →
Application:
08/489,550 →
Vehicle Drive Control System
Patent:
5,808,427 →
Application:
08/651,842 →
Control System for a Hybrid Vehicle
Patent:
5,898,282 →
Application:
08/910,572 →
Method and apparatus for adaptive hybrid vehicle control
Patent:
6,242,873 →
Application:
09/494,812 →
Battery Operating Condition Dependent Method and Apparatus for Controlling Energy Transfer Between an Energy Bus and a System of Batteries
Patent:
6,555,991 →
Application:
10/062,452 →
Switching System
Contactor Feedback and Precharge/Discharge Circuit
Process, Apparatus, Media and Signals for Controlling Operating Conditions of a Hybrid Electric Vehicle to Optimize Operating Characteristics of the Vehicle
Inverter-Filter Non-Linearity Blanking Time and Zero Current Clamping Compensation System and Method
Indirect Rotor Resistance Estimation System and Method
Filter Package
Non-Linear Droop Control System and Method for Isochronous Frequency Operation
Process and Apparatus for Reducing Nitrogen Oxide Emissions in Genset Systems
Rfi/Emi Filter for Variable Frequency Motor Drive System
Method, Apparatus, Signals, and Medium for Managing Power in a Hybrid Vehicle
Method, Apparatus, Signals, and Medium for Managing Power in a Hybrid Vehicle
Method and System for Multiphase Current Sensing
Method and Apparatus for Starting an Internal Combustion Engine
Methods of Supplying Energy to an Energy Bus in a Hybrid Electric Vehicle, and Apparatuses, Media and Signals for the Same
Method, Apparatus, Signals and Media, for Selecting Operating Conditions of a Genset
Method, Apparatus, Signals and Media, for Selecting Operating Conditions of a Genset
Method and Apparatus for Starting an Engine in a Hybrid Vehicle
Method of Fabricating Substrateless Thin Film Field-Effect Devices and an Organic Thin Film Transistor Obtainable by the Method
Field-Effect Device for the Detection of Small Quantities of Electric Charge, Such as Those Generated in Bio-Molecular Process, Bound in the Vicinity of the Surface
Method for Fabricating Complex Three-Dimensional Structures on the Submicrometric Scale by Combined Lithography of Two Resists
Normalization of Calling Party Sound Levels on a Conference Bridge
Patent:
5,724,416 →
Application:
08/672,767 →
Secure Method for Conferencing Through a Remote Pbx
Patent:
7,187,763 →
Application:
10/294,237 →
Method and Apparatus for Detecting and Correcting Electrical Interference in a Conference Call
Patent:
7,599,357 →
Application:
11/011,256 →
Method and Apparatus for Introducing a Delay During a Call Setup in a Communication Network
Patent:
7,613,113 →
Application:
11/239,759 →
Method and Apparatus for Bulletin Board Messaging in a Voice Mail System
Method and Apparatus for Bulletin Board Messaging in a Voice Mail System
Related Assignments
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Change of Address of Assignee
Apr 15, 2009
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Jan 10, 2012
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Reel/Frame 027512/0196 →
Change of Name
Mar 13, 2014
From: MOSAID TECHNOLOGIES INCORPORATED
To: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
Reel/Frame 032439/0638 →
Change of Name
Mar 17, 2014
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Release of Security Interest
Aug 7, 2014
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U.S. Patent Security Agreement (for Non-U.S. Grantors)
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Amended and Restated U.S. Patent Security Agreement (for Non-U.S. Grantors)
Aug 22, 2018
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Release of U.S. Patent Agreement (for Non-U.S. Grantors)
Oct 12, 2018
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Release of Security Interest
Oct 30, 2020
From: CPPIB CREDIT INVESTMENTS INC.
To: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
Reel/Frame 054263/0253 →
Release of Security Interest
Nov 2, 2020
From: CPPIB CREDIT INVESTMENTS INC.
To: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
Reel/Frame 054279/0198 →
Release of Security Interest
Nov 2, 2020
From: CPPIB CREDIT INVESTMENTS INC.
To: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
Reel/Frame 054278/0333 →
Release of Security Interest
Nov 2, 2020
From: CPPIB CREDIT INVESTMENTS INC.
To: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
Reel/Frame 054279/0001 →
Release of Security Interest
Nov 3, 2020
From: CPPIB CREDIT INVESTMENTS INC.
To: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
Reel/Frame 054310/0421 →
Change of Name
Jun 16, 2021
From: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
To: MOSAID TECHNOLOGIES INC.
Reel/Frame 056602/0990 →
Change of Name
Jun 16, 2021
From: CONVERSANT INTELLECTUAL PROPERTY INC.
To: MOSAID TECHNOLOGIES INCORPORATED
Reel/Frame 056602/0253 →
Change of Name
Sep 9, 2021
From: CONVERSANT INTELLECTUAL PROPERTY INC.
To: MOSAID TECHNOLOGIES INCORPORATED
Reel/Frame 057449/0162 →
Change of Name
Sep 9, 2021
From: CONVERSANT INTELLECTUAL PROPERTY INC.
To: MOSAID TECHNOLOGIES INCORPORATED
Reel/Frame 057449/0393 →
Assignment of Assignor's Interest
May 11, 2022
From: MOSAID TECHNOLOGIES INCORPORATED
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 059952/0976 →
Corrective Assignment to Correct the Conveying Party's Name Previously Recorded at Reel: 057449 Frame: 0393. Assignor(S) Hereby Confirms the Change of Name.
Aug 30, 2023
From: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
To: MOSAID TECHNOLOGIES INCORPORATED
Reel/Frame 064761/0404 →
Corrective Assignment to Correct the Conveying Party's Name Previously Recorded at Reel: 056602 Frame: 0253. Assignor(S) Hereby Confirms the Change of Name.
Aug 30, 2023
From: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
To: MOSAID TECHNOLOGIES INCORPORATED
Reel/Frame 064783/0267 →