Non-volatile semiconductor memory device with power saving feature
View Patent ↗A non-volatile semiconductor memory device, which comprises (i) an interface having an input for receiving an input clock and a set of data lines for receiving commands issued by a controller including an erase command; (ii) a module having circuit components in a feedback loop configuration and being driven by a reference clock; (iii) a clock control circuit capable of controllably switching between a first state in which the reference clock tracks the input clock and a second state in which the reference clock is decoupled from the input clock; and (iv) a command processing unit configured to recognize the commands and to cause the clock control circuit to switch from the first state to the second state in response to recognizing the erase command. The module consumes less power when the reference clock is decoupled from the input clock than when the reference clock tracks the input clock.
1. A non-volatile semiconductor memory device, comprising:
an interface comprising:
an input port for receiving an input clock signal; and
a set of data lines for receiving commands, including a program command, the commands issued by a controller;
a module having circuit components in a feedback loop configuration, the module being driven by a reference clock signal;
a clock control circuit capable of controllably switching between a first operational state in which the reference clock signal tracks the input clock signal and a second operational state in which the reference clock signal is decoupled from the input clock signal; and
a command processing unit configured to recognize the commands issued by the controller and to cause the clock control circuit to switch from the first operational state to the second operational state in response to recognizing the program command;
wherein when the reference clock signal tracks the input clock signal, the module consumes a first amount of power and wherein when the reference clock signal is decoupled from the input clock signal, the module consumes a second amount of power that is less than the first amount of power.
2. The non-volatile semiconductor memory device defined in claim 1 , further comprising control circuitry for outputting a signal indicative that the device is busy in response to the command processing unit recognizing the program command.
3. The non-volatile semiconductor memory device defined in claim 2 , wherein the control circuitry is configured to output the signal indicative that the device is busy after the command processing unit causes the clock control circuit to switch from the first operational state to the second operational state.
4. The non-volatile semiconductor memory device defined in claim 1 , wherein the command processing unit is configured to start a program operation in response to receipt of the program command.
5. The non-volatile semiconductor memory device defined in claim 4 , wherein the command processing unit is configured to cause the clock control circuit to switch back to the first operational state after the program operation is complete.
6. The non-volatile semiconductor memory device defined in claim 5 , further comprising control circuitry configured to issue a signal indicating that the device is ready after the program operation is complete.
7. The non-volatile semiconductor memory device defined in claim 6 , wherein the clock control circuit comprises a delay locked loop that loses synchronization when the reference clock signal is decoupled from the input clock signal, wherein the signal indicating that the device is ready is issued after the delay locked loop has regained synchronization following the clock control circuit having switched back to the first operational state.
8. The non-volatile semiconductor memory device defined in claim 4 , wherein the command processing unit is configured to cause the clock control circuit to switch back to the first operational state before the program operation is complete.
9. The non-volatile semiconductor memory device defined in claim 8 , further comprising control circuitry configured to issue a signal indicating that the device is ready after the command processing unit causes the clock control circuit to switch back to the first operational state.
10. The non-volatile semiconductor memory device defined in claim 8 , wherein the clock control circuit comprises a delay locked loop that loses synchronization when the reference clock signal is decoupled from the input clock signal, wherein the signal indicating that the device is ready is issued after the delay locked loop has regained synchronization following the clock control circuit having switched back to the first operational state.
11. The non-volatile semiconductor memory device defined in claim 1 , further comprising a plurality of non-volatile memory cells, wherein the command processing unit is configured to cause the clock control circuit to switch back to the first operational state after at least some of the non-volatile memory cells have been programmed.
12. The non-volatile semiconductor memory device defined in claim 1 , wherein the module comprises a clock synchronization circuit configured to generate a synchronizing clock signal based on the reference clock signal, wherein the clock synchronization circuit comprises at least one of a delay locked loop and a phase locked loop.
13. The non-volatile semiconductor memory device defined in claim 1 , wherein the clock control circuit implements a logic AND function producing an output corresponding to the reference clock signal, wherein the logic AND function has a first input corresponding to the input clock signal and a second input corresponding to a signal that is asserted when the program command is recognized by the command processing unit.
14. The non-volatile semiconductor memory device defined in claim 1 , wherein the program command is a PAGE PROGRAM command.
15. The non-volatile semiconductor memory device defined in claim 1 , wherein the interface comprises an input port for receiving a device select signal from the controller, wherein the command processing unit is configured to allow the clock control circuit to switch to the second operational state even when the device select signal is indicative of the device having been selected.
16. The non-volatile semiconductor memory device defined in claim 1 , wherein the interface comprises an input port for receiving a device select signal from the controller, wherein the command processing unit is configured to prevent the clock control circuit from switching to the second operational state unless the device select signal is indicative of the device having been deselected.
17. The non-volatile semiconductor memory device defined in claim 1 , wherein when the reference clock signal tracks the input clock signal, the module effects a first average number of signal transitions per unit time and wherein when the reference clock signal is decoupled from the input clock signal, the module effects a second average number of signal transitions per unit time that is less than the first average number of signal transitions per unit time.
18. The non-volatile semiconductor memory device defined in claim 1 , implemented as a phase-change memory device.
19. A non-volatile semiconductor memory device, comprising:
first means for providing an input clock signal;
a module having circuit components in a feedback loop configuration and being driven by a reference clock signal;
second means for controllably switching between a first operational state in which the reference clock signal tracks the input clock signal and a second operational state in which the reference clock signal is decoupled from the input clock signal; and
third means for recognizing commands issued by a controller, including a program command, and varying the operational state of the second means in response to recognizing the program command;
wherein when the reference clock signal tracks the input clock signal, the module consumes a first amount of power and wherein when the reference clock signal is decoupled from the input clock signal, the module consumes a second amount of power that is less than the first amount of power.
20. A method implemented by a non-volatile semiconductor memory device that is provided with an input clock signal and that comprises a module with circuit components in a feedback loop configuration, the circuit components being driven by a reference clock signal, comprising:
producing the reference clock signal such that it follows the input clock signal in a first operational state of the device and such that it is decoupled from the input clock signal in a second operational state of the device, wherein when the reference clock signal follows the input clock signal, the module consumes a first amount of power and wherein when the reference clock signal is decoupled from the input clock signal, the module consumes a second amount of power that is less than the first amount of power; and
causing the device to switch from the first operational state to the second operational state in response to recognizing a program command received from a controller.
21. A system, comprising:
a controller configured to issue a master clock signal and to issue commands including a program command; and
a non-volatile semiconductor memory device, which comprises:
an interface comprising:
an input port for receiving an input clock signal related to the master clock signal; and
a set of data lines for receiving the commands issued by the controller;
a module having circuit components in a feedback loop configuration, the module being driven by a reference clock signal;
a clock control circuit capable of controllably switching between a first operational state in which the reference clock signal tracks the input clock signal and a second operational state in which the reference clock signal is decoupled from the input clock signal; and
a command processing unit configured to recognize the commands issued by the controller and to cause the clock control circuit to switch from the first operational state to the second operational state in response to recognizing the program command;
wherein when the reference clock signal tracks the input clock signal, the module consumes a first amount of power and wherein when the reference clock signal is decoupled from the input clock signal, the module consumes a second amount of power that is less than the first amount of power.