Patent Assignment
Reel/Frame 046900/0136
Amended and Restated U.S. Patent Security Agreement (for Non-U.S. Grantors)
Recorded: 2018-08-22
Pages: 125
Assignor
CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
Executed: 2018-07-31
Assignee
CPPIB CREDIT INVESTMENTS, INC.
ONE QUEEN STREET EAST, TORONTO, M5C 2W5, CANADA
Covered Properties
(1133)
Bi-Directional Data Bus Scheme with Optimized Read and Write Characters
Patent:
6,134,153 →
Application:
09/364,181 →
Bi-Directional Data Bus Scheme with Optimized Read and Write Characters
Patent:
5,982,674 →
Application:
09/163,341 →
Semiconductor Memory Asynchronous Pipeline
Semiconductor Memory Asynchronous Pipeline
Semiconductor Memory Asynchronous Pipeline
Semiconductor Memory Asynchronous Pipeline
Semiconductor Memory Asynchronous Pipeline
Semiconductor Memory Asynchronous Pipeline
Semiconductor Memory Asynchronous Pipeline
Semiconductor Memory Asynchronous Pipeline
Regulated Dram Cell Plate and Precharge Voltage Generator
Patent:
6,057,676 →
Application:
09/099,464 →
Process, Voltage, Temperature Independent Switched Delay Compensation Scheme
Process, Voltage, Temperature Independent Switched Delay Compensation Scheme
Process, Voltage, Temperature Independent Switched Delay Compensation Scheme
Patent:
6,327,318 →
Application:
09/106,755 →
High Bandwidth Memory Interface
High Bandwidth Memory Interface
High Bandwidth Memory Interface
High Bandwidth Memory Interface
High Bandwidth Memory Interface
Apparatuses for Synchronous Transfer of Information
High Bandwidth Memory Interface
Column Redundancy Circuit with Reduced Signal Path Delay
Patent:
6,137,735 →
Application:
09/182,495 →
Dynamic Content Addressable Memory Cell
Dynamic content addressable memory cell
Patent:
6,320,777 →
Application:
09/533,128 →
Method and Apparatus for Providing a Packet Buffer Random Access Memory
Frequency-Doubling Delay Locked Loop
Frequency-Doubling Delay Locked Loop
Frequency-Doubling Delay Locked Loop
Frequency-Doubling Delay Locked Loop
Frequency-Doubling Delay Locked Loop
Frequency-Doubling Delay Locked Loop
Frequency-Doubling Delay Locked Loop
Patent:
6,441,659 →
Application:
09/562,024 →
Link Aggregation
Link Aggregation
Patent:
6,765,866 →
Application:
09/516,001 →
Multi-Stage Lookup for Translating Between Signals of Different Bit Lengths
Multi-stage lookup for translating between signals of different bit lengths
Patent:
6,384,750 →
Application:
09/533,724 →
Port Packet Queuing
Port Packet Queuing
Port Packet Queuing
Patent:
7,236,489 →
Application:
09/559,190 →
Matchline Sense Circuit and Method
Matchline Sense Circuit and Method
Method and Apparatus for Providing Input Back Pressure in an Output Buffered Switch
Patent:
6,856,595 →
Application:
09/574,621 →
Searchline Control Circuit and Power Reduction Method
Method and Apparatus for Simultaneous Differential Data Sensing and Capture in a High Speed Memory
Method and Apparatus for Synchronization of Row and Column Access Operations
Method and Apparatus for Synchronization of Row and Column Access Operations
Method and Apparatus for Synchronization of Row and Column Access Operations
Method and Apparatus for Synchronization of Row and Column Access Operations
Method and Apparatus for Synchronization of Row and Column Access Operations
Method and Apparatus for Synchronization of Row and Column Access Operations
Method and Apparatus for Synchronization of Row and Column Access Operations
High Speed Dram Architecture with Uniform Access Latency
High Speed Dram Architecture with Uniform Access Latency
High Speed Dram Architecture with Uniform Access Latency
High Speed Dram Architecture with Uniform Access Latency
High Speed Dram Architecture with Uniform Access Latency
Method and Apparatus for Reducing Pool Starvation in a Shared Memory Switch
Method and Apparatus for Reducing Pool Starvation in a Shared Memory Switch
Method and Apparatus for Reducing Pool Starvation in a Shared Memory Switch
Method and Apparatus for Reducing Pool Starvation in a Shared Memory Switch
Method and Apparatus for Reducing Pool Starvation in a Shared Memory Switch
Method and Apparatus for Reducing Pool Starvation in a Shared Memory Switch
Method and Apparatus for Reducing Pool Starvation in a Shared Memory Switch
Patent:
7,007,071 →
Application:
09/624,276 →
Method and Apparatus for Searching a Filtering Database with One Search Operation
Patent:
6,633,567 →
Application:
09/652,196 →
Method and Apparatus for Accelerating Retrieval of Data from a Memory System with Cache by Reducing Latency
Method and Apparatus for Reducing Latency in a Memory System
Method and Apparatus for Selectively Disabling Logic in a Semiconductor Device
Patent:
6,434,077 →
Application:
09/804,988 →
Bitline Precharge
Cascaded Charge Pump Power Supply
Content Addressable Memory Cell Having Improved Layout
Content Addressable Memory Cell Having Improved Layout
Digitally Controlled Pulse Width Adjusting Circuit
Patent:
6,538,465 →
Application:
10/084,620 →
Matchline Sensing for Content Addressable Memories
Low Power Content Addressable Memory Architecture
Patent:
6,584,003 →
Application:
10/134,753 →
Trunking in a Matrix
Method and System for Packet Encryption
Method and System for Packet Processing
Method and System for Packet Processing
Method and System for Packet Encryption
Congestion Level Management in a Network Device
Congestion Management in a Network
Method and Apparatus for Reordering Entries in a Multi Probe Lookup
Sorting Method and Apparatus Using a Cam
Sorting Method and Apparatus Using a Cam
Sorting Method and Apparatus Using a Cam
Content Addressable Memory Architecture
Content Addressable Memory Architecture
Method and Apparatus for Interconnecting Content Addressable Memory Devices
Method for allocating processor resources and system for encrypting data
Method and Apparatus for Replacing Defective Rows in a Semiconductor Memory Array
Block Programmable Priority Encoder in a Cam
Block Programmable Priority Encoder in a Cam
Patent:
43,552 →
Application:
12/709,198 →
Wide Frequency Range Delay Locked Loop
Wide Frequency Range Delay Locked Loop
Wide Frequency Range Delay Locked Loop
Wide Frequency Range Delay Locked Loop
Wide Frequency Range Delay Locked Loop
Wide Frequency Range Delay Locked Loop
Synchronization Circuit and Method with Transparent Latches
Double Data Rate Output Latch for Static Ram Device Has Edge-Triggered Flip-Flop to Output Ddr Signal to Synchronize with a Second Clock Signal
Double Data Rate Output Circuit and Method
Double Data Rate Output Circuit
Synchronization Circuit and Method with Transparent Latches
Timing Vernier Using a Delay Locked Loop
Timing Vernier Using a Delay Locked Loop
Timing Vernier Using a Delay Locked Loop
Start Up Circuit for Delay Locked Loop
Initialization Circuit for Delay Locked Loop
Initialization Circuit for Delay Locked Loop
Start Up Circuit for Delay Locked Loop
Mismatch-Dependent Power Allocation Technique for Match-Line Sensing in Content-Addressable Memories
Low Power Match-Line Sensing Circuit
Compare Circuit for a Content Addressable Memory Cell
Ternary Cam Cell for Reduced Matchline Capacitance
Charge Pump for Pll/Dll
Charge Pump for Pll/Dll
Charge Pump for Pll/Dll
Charge Pump for Pll/Dll
Charge Pump for Pll/Dll
Charge Pump for Pll/Dll
High Output Impedance Charge Pump for Pll/Dll
Charge Pump for Pll/Dll
Patent:
47,715 →
Application:
14/334,347 →
Clock Logic Domino Circuits for High-Speed and Energy Efficient Microprocessor Pipelines
Delay Locked Loop Circuit and Method
Method and Apparatus for Initializing a Delay Locked Loop
Delay Locked Loop Circuit and Method
Patent:
43,947 →
Application:
13/105,749 →
Delay Locked Loop Circuit and Method
Voltage Down Converter for High Speed Memory
Voltage Down Converter for High Speed Memory
Voltage Down Converter for High Speed Memory
Semiconductor Integrated Circuit Having Current Leakage Reduction Scheme
Power Up Circuit with Low Power Sleep Mode Operation
Flash Memory Device with Data Output Control
Method and System for Accessing a Flash Memory Device
Method and System for Accessing a Flash Memory Device
Method and System for Accessing a Flash Memory Device
Method and System for Accessing a Flash Memory Device
Method and System for Accessing a Flash Memory Device
Method and System for Accessing a Flash Memory Device
Multiple Independent Serial Link Memory
Semiconductor Integrated Circuit Having Low Power Consumption with Self-Refresh
Dynamic Random Access Memory Device and Method for Self-Refreshing Memory Cells
Dynamic Random Access Memory Device and Method for Self-Refreshing Memory Cells
Dynamic Random Access Memory Device and Method for Self-Refreshing Memory Cells
Dynamic Random Access Memory Device and Method for Self-Refreshing Memory Cells
Power Managers for an Integrated Circuit
Power Managers for an Integrated Circuit
Power Managers for an Integrated Circuit
Power Managers for an Integrated Circuit
Power Managers for an Integrated Circuit
Power Managers for an Integrated Circuit
Power Managers for an Integrated Circuit
Power Managers for an Integrated Circuit
Managing Power on Integrated Circuits Using Power Islands
Power Managers for an Integrated Circuit
Application:
15/192,486 →
Low Leakage and Data Retention Circuitry
Low Leakage and Data Retention Circuitry
Low Leakage and Data Retention Circuitry
Low Leakage and Data Retention Circuitry
Low Leakage and Data Retention Circuitry
Low Leakage and Data Retention Circuitry
Low Leakage and Data Retention Circuitry
Low Leakage and Data Retention Circuitry
Low Leakage and Data Retention Circuitry
Systems and Methods for Minimizing Static Leakage of an Integrated Circuit
Systems and Methods for Minimizing Static Leakage of an Integrated Circuit
Systems and Methods for Minimizing Static Leakage of an Integrated Circuit
Systems and Methods for Minimizing Static Leakage of an Integrated Circuit
Systems and Methods for Minimizing Static Leakage of an Integrated Circuit
Systems and Methods for Minimizing Static Leakage of an Integrated Circuit
Patent:
48,410 →
Application:
14/209,455 →
Phase-Locked Loop Circuitry Using Charge Pumps with Current Mirror Circuitry
Integrated Circuit with Signal Bus Formed by Cell Abutment of Logic Cells
Integrated Circuit with Signal Bus Formed by Cell Abutment of Logic Cells
Asic Design Using Clock and Power Grid Standard Cell
Sram Leakage Reduction Circuit
Sram Leakage Reduction Circuit
Sram Leakage Reduction Circuit
Non-Volatile Memory Bank and Page Buffer Therefor
Non-Volatile Memory Bank and Page Buffer Therefor
Non-Volatile Memory Serial Core Architecture
Non-Volatile Memory Serial Core Architecture
Non-Volatile Memory Serial Core Architecture
Flash Memory System Control Scheme
Non-Volatile Semiconductor Memory with Page Erase
Non-Volatile Semiconductor Memory with Page Erase
Non-Volatile Semiconductor Memory with Page Erase
Non-Volatile Semiconductor Memory with Page Erase
Flash Multi-Level Threshold Distribution Scheme
Flash Multi-Level Threshold Distribution Scheme
Flash Multi-Level Threshold Distribution Scheme
Flash Multi-Level Threshold Distribution Scheme
Flash Multi-Level Threshold Distribution Scheme
Flash Multi-Level Threshold Distribution Scheme
Low Power Memory Architecture
Low Power Memory Architecture
Dynamic Random Access Memory Device and Method for Self-Refreshing Memory Cells with Temperature Compensated Self-Refresh
Dynamic Random Access Memory Device and Method for Self-Refreshing Memory Cells with Temperature Compensated Self-Refresh
Dynamic Random Access Memory Device and Method for Self-Refreshing Memory Cells with Temperature Compensated Self-Refresh
Dynamic Random Access Memory Device and Method for Self-Refreshing Memory Cells with Temperature Compensated Self-Refresh
Dynamic Random Access Memory Device and Method for Self-Refreshing Memory Cells with Temperature Compensated Self-Refresh
Dynamic Random Access Memory with Fully Independent Partial Array Refresh Function
Dynamic Random Access Memory with Fully Independent Partial Array Refresh Function
Dynamic Random Access Memory with Fully Independent Partial Array Refresh Function
Dynamic Random Access Memory with Fully Independent Partial Array Refresh Function
Dynamic Random Access Memory with Fully Independent Partial Array Refresh Function
Dynamic Random Access Memory with Fully Independent Partial Array Refresh Function
Flash Memory Program Inhibit Scheme
Flash Memory Program Inhibit Scheme
Flash Memory Program Inhibit Scheme
Flash Memory Program Inhibit Scheme
A Double Data Rate Converter Circuit Includes a Delay Locked Loop for Providing the Plurality of Clock Phase Signals
Apparatus and Method for Interfacing to a Memory
Synchronous Memory Read Data Capture
Synchronous Memory Read Data Capture
Patent:
46,819 →
Application:
14/141,686 →
Daisy Chain Cascading Devices
Asynchronous Id Generation
Hybrid Solid-State Memory System Having Volatile and Non-Volatile Memory
Hybrid Solid-State Memory System Having Volatile and Non-Volatile Memory
Hybrid Solid-State Memory System Having Volatile and Non-Volatile Memory
Independent Link and Bank Selection
Independent Link and Bank Selection
Independent Link and Bank Selection
Memory with Output Control
Memory with Output Control
Non-Volatile Memory Device
Memory with Output Control
Memory with Output Control
Memory with Output Control
Memory with Output Control
Flash Memory System
Flash Memory System
Flash Memory Device
Memory with Output Control
Error Correction Scheme for Memory
Error Correction Scheme for Memory
Memory System and Method with Serial and Parallel Modes
Memory System and Method with Serial and Parallel Modes
Circuit for Clamping Current in a Charge Pump
Circuit for Clamping Current in a Charge Pump
Circuit for Clamping Current in a Charge Pump
Circuit for Clamping Current in a Charge Pump
Circuit for Clamping Current in a Charge Pump
Circuit for Clamping Current in a Charge Pump
Circuit for Clamping Current in a Charge Pump
Circuit for Clamping Current in a Charge Pump
Delay Locked Loop Circuit
Delay Locked Loop Circuit
Delay Locked Loop Circuit
Phase Detector Circuit and Method Therefor
Decoding Control with Address Transition Detection in Page Erase Function
System and Method of Page Buffer Operation for Memory Devices
System and Method of Page Buffer Operation for Memory Devices
Non-Volatile Memory with Dynamic Multi-Mode Operation
Non-Volatile Memory with Dynamic Multi-Mode Operation
Non-Volatile Memory with Dynamic Multi-Mode Operation
Non-Volatile Memory with Dynamic Multi-Mode Operation
Non-Volatile Memory with Dynamic Multi-Mode Operation
Simplified Bias Circuitry for Differential Buffer Stage with Symmetric Loads
Bias Generator Providing for Low Power, Self-Biased Delay Element and Delay Line
Voltage Level Shifter and Buffer Using Same
Source Side Asymmetrical Precharge Programming Scheme
Source Side Asymmetrical Precharge Programming Scheme
Source Side Asymmetrical Precharge Programming Scheme
Modular Command Structure for Memory and Memory System
Balanced Pseudo-Random Binary Sequence Generator
Dynamic Impedance Control for Input/Output Buffers
Dynamic Impedance Control for Input/Output Buffers
Dynamic Impedance Control for Input/Output Buffers
Dynamic Impedance Control for Input/Output Buffers
Application:
15/079,085 →
Publication:
US US20160277027A1
Dynamic Impedance Control for Input/Output Buffers
Dynamic Impedance Control for Input/Output Buffers
Memory with Data Control
Storage of Data in Memory via Packet Strobing
Apparatus and Method of Page Program Operation for Memory Devices with Mirror Back-Up of Data
Apparatus and Method of Page Program Operation for Memory Devices with Mirror Back-Up of Data
Memory System Having Incorrupted Strobe Signals
Memory System Having Incorrupted Strobe Signals
Dynamic Random Access Memory and Boosted Voltage Producer Therefor
Application:
14/828,725 →
Publication:
US US20160035407A1
Dynamic Random Access Memory and Boosted Voltage Producer Therefor
Dynamic Random Access Memory and Boosted Voltage Producer Therefor
Dynamic Random Access Memory and Boosted Voltage Producer Therefor
Multi-Level Cell Access Buffer with Dual Function
Multi-Level Cell Access Buffer with Dual Function
Multi-Level Cell Access Buffer with Dual Function
Pre-Charge Voltage Generation and Power Saving Modes
Pre-Charge Voltage Generation and Power Saving Modes
Pre-Charge Voltage Generation and Power Saving Modes
Pre-Charge Voltage Generation and Power Saving Modes
Partial Block Erase Architecture for Flash Memory
Partial Block Erase Architecture for Flash Memory
Non-Volatile Semiconductor Memory Having Multiple External Power Supplies
Non-Volatile Semiconductor Memory Having Multiple External Power Supplies
Patent:
8,300,471 →
Application:
13/096,874 →
Non-Volatile Semiconductor Memory Having Multiple External Power Supplies
Non-Volatile Semiconductor Memory Having Multiple External Power Supplies
Non-Volatile Semiconductor Memory Having Multiple External Power Supplies
Non-Volatile Semiconductor Memory Having Multiple External Power Supplies
Non-Volatile Semiconductor Memory Having Multiple External Power Supplies
Non-Volatile Semiconductor Memory Having Multiple External Power Supplies
Data processing with time-based memory access
Scalable Memory System
Clock Mode Determination in a Memory System
Clock Mode Determination in a Memory System
Clock Mode Determination in a Memory System
Clock Mode Determination in a Memory System
Clock Mode Determination in a Memory System
Clock Mode Determination in a Memory System
Clock Mode Determination in a Memory System
Clock Mode Determination in a Memory System
Clock Mode Determination in a Memory System
Clock Mode Determination in a Memory System
Apparatus and Method for Modeling Coarse Stepsize Delay Element and Delay Locked Loop Using Same
Apparatus and Method for Modeling Coarse Stepsize Delay Element and Delay Locked Loop Using Same
System and Method of Operating Memory Devices of Mixed Type
Nonvolatile Semiconductor Memory Device
Nonvolatile Memory Having Non-Power of Two Memory Capacity
Method for Stacking Serially-Connected Integrated Circuits and Multi-Chip Device Made from Same
Method for Stacking Serially-Connected Integrated Circuits and Multi-Chip Device Made from Same
Hierarchical Common Source Line Structure in Nand Flash Memory
Hierarchical Common Source Line Structure in Nand Flash Memory
Hierarchical Common Source Line Structure in Nand Flash Memory
Multiple Bit Per Cell Non Volatile Memory Apparatus and System Having Polarity Control and Method of Programming Same
Multiple-Bit Per Cell (Mbc) Non-Volatile Memory Apparatus and System Having Polarity Control and Method of Programming Same
Multiple-Bit Per Cell (Mbc) Non-Volatile Memory Apparatus and System Having Polarity Control and Method of Programming Same
Mulitple-Bit Per Cell (Mbc) Non-Volatile Memory Apparatus and System Having Polarity Control and Method of Programming Same
Dual Function Compatible Non-Volatile Memory Device
Dual Function Compatible Non-Volatile Memory Device
Dual Function Compatible Non-Volatile Memory Device
Dual Function Compatible Non-Volatile Memory Device
Non-Volatile Semiconductor Memory Device with Power Saving Feature
Non-Volatile Semiconductor Memory Device with Power Saving Feature
Non-Volatile Semiconductor Memory Device with Power-Saving Feature
Non-Volatile Semiconductor Memory Device with Power Saving Feature
Nand Flash Memory Having Multiple Cell Substrates
Nand Flash Memory Having Multiple Cell Substrates
Nand Flash Memory Having Multiple Cell Substrates
Nand Flash Memory Having Multiple Cell Substrates
Nand Flash Memory Having Multiple Cell Substrates
Power Supplies in Flash Memory Devices and Systems
Power Supplies in Flash Memory Devices and Systems
Power Supplies in Flash Memory Devices and Systems
Non-Volatile Memory Device Having Configurable Page Size
Non-Volatile Memory Device Having Configurable Page Size
Non-Volatile Memory Device Having Configurable Page Size
Non-Volatile Memory Device Having Configurable Page Size
Non-Volatile Memory Device Having Configurable Page Size
Data Storage and Stackable Chip Configurations
Data Storage and Stackable Configurations
Flexible Memory Operations in Nand Flash Devices
Flexible Memory Operations in Nand Flash Devices
Cache Filtering Method and Apparatus
Bridge Device Architecture for Connecting Discrete Memory Devices to a System
Bridge Device Architecture for Connecting Discrete Memory Devices to a System
Composite Memory Having a Bridging Device for Connecting Discrete Memory Devices to a System
Stacked Semiconductor Devices Including a Master Device
Stacked Semiconductor Devices Including a Master Device
Stacked Semiconductor Devices Including a Master Device
Stacked Semiconductor Devices Including a Master Device
Nand Flash Architecture with Multi-Level Row Decoding
Nand Flash Architecture with Multi-Level Row Decoding
Bridge Device Architecture for Connecting Discrete Memory Devices to a System
Bridge Device Architecture for Connecting Discrete Memory Devices to a System
Bridge Device Having a Virtual Page Buffer
Application:
12/607,680 →
Publication:
US US20100115172A1
Bridging Device Having a Configurable Virtual Page Size
Bridging Device Having a Configurable Virtual Page Size
Using Interrupted Through-Silicon-Vias in Integrated Circuits Adapted for Stacking
Using Interrupted Through-Silicon-Vias in Integrated Circuits Adapted for Stacking
Using Interrupted Through-Silicon-Vias in Integrated Circuits Adapted for Stacking
Using Interrupted Through-Silicon-Vias in Integrated Circuits Adapted for Stacking
System and Method Providing Interoperability Between Cellular and Other Wireless Systems
System and Method Providing Interoperability Between Cellular and Other Wireless Systems
Reconfiguring Through Silicon Vias in Stacked Multi-Die Packages
Reconfiguring Through Silicon Vias in Stacked Multi-Die Packages
Phase Change Memory Word Line Driver
Phase Change Memory Word Line Driver
Semiconductor Memory Device with Plural Memory Die and Controller Die
Semiconductor Memory Device with Plural Memory Die and Controller Die
Multi-Chip Package with Offset Die Stacking and Method of Making Same
Multi-Chip Package with Offset Die Stacking
Composite Semiconductor Memory Device with Error Correction
Composite Semiconductor Memory Device with Error Correction
Method of Configuring Non-Volatile Memory for a Hybrid Disk Drive
Method of Configuring Non-Volatile Memory for a Hybrid Disk Drive
Phase-Change Memory with Multiple Polarity Bits Having Enhanced Endurance and Error Tolerance
Semiconductor Memory Device with Sense Amplifier and Bitline Isolation
Semiconductor Memory Device with Sense Amplifier and Bitline Isolation
Semiconductor Device with Through-Silicon Vias
Multi-Chip Package with Thermal Frame and Method of Assembling
Semiconductor Device with Configurable Through-Silicon Vias
Multipage Program Scheme for Flash Memory
Multipage Program Scheme for Flash Memory
Error Detection and Correction Codes for Channels and Memories with Incomplete Error Characteristics
Method and Apparatus for Sharing Internal Power Supplies in Integrated Circuit Devices
Method and Apparatus for Sharing Internal Power Supplies in Integrated Circuit Devices
Memory System and Method Using Stacked Memory Device Dice
Memory System and Method Using Stacked Memory Device Dice
Voltage Regulation for 3D Packages and Method of Manufacturing Same
Memory System with a Layer Comprising a Dedicated Redundancy Area
Flash Memory System
Flash Memory System
Interposer for Stacked Semiconductor Devices
Reduced Noise Dram Sensing
Cpu with Stacked Memory
Device Selection Schemes in Multi Chip Package Nand Flash Memory System
Device Selection Schemes in Multi Chip Package Nand Flash Memory System
Split Block Decoder for a Nonvolatile Memory Device
Split Block Decoder for a Nonvolatile Memory Device
Power Saving in Wireless Network Entities
Power Saving in Wireless Network Entities
Integrated Erase Voltage Path for Multiple Cell Substrates in Nonvolatile Memory Devices
Integrated Erase Voltage Path for Multiple Cell Substrates in Nonvolatile Memory Devices
Method and System for Programming Non-Volatile Memory with Junctionless Cells
Nand Flash Memory with Vertical Cell Stack Structure and Method for Manufacturing Same
Nonvolatile Memory with Split Substrate Select Gates and Heirarchical Bitline Configuration
Structure and Method for Manufacture of Memory Device with Thin Silicon Body
Structure and Method for Manufacture of Memory Device with Thin Silicon Body
Lithography-friendly Local Read Circuit for NAND Flash Memory Devices and Manufacturing Method Thereof
Lithography-friendly Local Read Circuit for NAND Flash Memory Devices and Manufacturing Method Thereof
U-Shaped Common-Body Type Cell String
U-Shaped Common-Body Type Cell String
U-Shaped Common-Body Type Cell String
Through Semiconductor via Structure with Reduced Stress Proximity Effect
Application:
14/312,052 →
Publication:
US US20150021773A1
Vertical Gate Stacked Nand and Row Decoder for Erase Operation
Vertical Gate Stacked Nand and Row Decoder for Erase Operation
Cell Array with a Manufacturable Select Gate for a Nonvolatile Semiconductor Memory Device
Cost Effective Method of Forming Embedded Dram Capacitor
System and Method for Controlling a Wireless Network
Three Dimensional Nonvolatile Memory Cell Structure with Upper Body Connection
Three-Dimensional Nonvolatile Memory Cell Structure with Upper Body Connection
Patent:
47,816 →
Application:
15/869,245 →
Nonvolatile Semiconductor Memory Device
Memory Device with Manufacturable Cylindrical Storage Node
Memory Device with Manufacturable Cylindrical Storage Node
Memory Device with Manufacturable Cylindrical Storage Node
DRAM Memory Device with Manufacturable Capacitor
Scheduling Systems and Methods for Wireless Networks
System and Method for Frequency Synchronization of Doppler-Shifted Subcarriers
Relay Systems and Methods for Wireless Networks
Relay Systems and Methods for Wireless Networks
Access Transistor of a Nonvolatile Memory Device and Method for Fabricating Same
Temperature-Dependent Refresh Cycle for Dram
Synchronous Feedback Digital Circuit Having a Minimzed Switching Power Loss
Patent:
6,400,194 →
Application:
09/642,332 →
Method and Apparatus for Determining Interpolated Intermediate Values of a Sampled Signal
Integrated Circuit Configuration for Testing Transistors, and a Semiconductor Wafer Having Such a Circuit Configuration
Apparatus and Method for Patterning a Semiconductor Wafer
Delay Locked Loop
Measurement Probe for Detecting Electrical Signals in an Integrated Semiconductor Circuit
Method for Releasable Contact-Connection of a Plurality of Integrated Semiconductor Modules on a Wafer
Asynchronous SRAM compatible memory device using DRAM cell and method for driving the same
Synchronous Sram-Compatible Memory and Method of Driving the Same
Frequency Division Multiplexing System with Selectable Rate
Frequency Division Multiplexing System with Selectable Rate
Frequency Division Multiplexing System with Selectable Rate
Frequency Division Multiplexing System with Selectable Rate
Frequency Division Multiplexing System with Selectable Rate
Frequency Division Multiplexing System with Selectable Rate
Orthogonal Frequency Division Multiplexing System with Selectable Rate
Patent:
6,563,786 →
Application:
09/224,695 →
Error Screening Based on Code and Control Information Consistency in a Communication System
Patent:
6,662,339 →
Application:
09/464,042 →
Binary-Ternary Content Addressable Memory
Patent:
6,362,992 →
Application:
09/684,589 →
Dynamic Linking of Banks in Configurable Content Addressable Memory Systems
Cascading Content Addressable Memory Devices with Programmable Input / Output Connections
Determining the Position of a Constant Frequency Interval in a Telecommunication Signal
Patent:
6,937,672 →
Application:
09/515,224 →
Method and Device for Robust Fallback in Data Communication Systems
Processing System Having Sequential Address Indicator Signals
Patent:
7,124,281 →
Application:
09/667,122 →
Data Processing System Having Redirecting Circuitry and Method Therefor
Controller and Method for Controlling an Ignition Coil
Instruction for Conditionally Yielding to a Ready Thread Based on Priority Criteria
Address Translation Trace Message Generation for Debug
Program Correlation Message Generation for Debug
Communications and Control Network Having Multiple Power Supplies
Patent:
6,396,391 →
Application:
09/141,321 →
Local Area Network for Distributing Data Communication, Sensing and Control Signals
Local Area Network for Distributing Data Communication, Sensing and Control Signals
Local Area Network for Distributing Data Communication, Sensing and Control Signals
Local Area Network for Distributing Data Communication, Sensing and Control Signals
Patent:
6,956,826 →
Application:
09/349,020 →
Networks for Telephony and Data Communication
Network for Telephony and Data Communication
Network for Telephony and Data Communication
Telephone Outlet for Implementing a Local Area Network Over Telephone Lines and a Local Area Network Using Such Outlets
Telephone Outlet for Implementing a Local Area Network Over Telephone Lines and a Local Area Network Using Such Outlets
A Telephone Outlet for Implementing a Local Area Network Over Telephone Lines and a Local Area Network Using Such Outlets
Telephone Outlet for Implementing a Local Area Network Over Telephone Lines and a Local Area Network Using Such Outlets
Patent:
6,549,616 →
Application:
09/531,692 →
Network Combining Wired and Non-Wired Segments
Network Combining Wired and Non-Wired Segments
Network Combining Wired and Non-Wired Segments
Network Combining Wired and Non-Wired Segments
Network Combining Wired and Non-Wired Segments
Network Combining Wired and Non-Wired Segments
Network Combining Wired and Non Wired Segments
Network Combining Wired and Non-Wired Segments
Network Combining Wired and Non-Wired Segments
Network Combining Wired and Non-Wired Segments
Network Combining Wired and Non-Wired Segments
Telephone Communication System Over a Single Telephone Line
Telephone Communication System Over a Single Telephone Line
Telephone Communication System Over a Single Telephone Line
Telephone Communication System Over a Single Telephone Line
Telephone Communication System Over a Single Telephone Line
Telephone Communication System Over a Single Telephone Line
Telephone Communication System Over a Single Telephone Line
Patent:
7,106,721 →
Application:
09/594,765 →
Telephone Communication System and Method Over Local Area Network Wiring
Telephone Communication System and Method Over Local Area Network Wiring
Communication System and Method Over Local Area Network Wiring
Telephone Communication System and Method Over Local Area Network Wiring
Telephone Communication System and Method Over Local Area Network Wiring
Patent:
6,961,303 →
Application:
09/666,856 →
System for Transmission Line Termination by Signal Cancellation
System and Method for Transmission-Line Termination by Signal Cancellation, and Applications Thereof
Method and Telephone Outlet for Allowing Telephone and Data Equipment to Be Connected to a Telephone Line via a Common Connector
Patent:
6,560,319 →
Application:
09/764,342 →
Telephone Outlet with Packet Telephony Adaptor, and a Network Using Same
Telephone Outlet with Packet Telephony Adapter, and a Network Using Same
Telephone Outlet with Packet Telephony Adapter, and a Network Using Same
Adapter for Mounting a Faceplate of a First Style on to an Electrical Outlet Cavity of a Second Style
Adapter for Mounting a Faceplate of a First Style to an Electrical Outlet Cavity of a Second Style
Adapter for Mounting a Faceplate of a First Style to an Electrical Outlet Cavity of a Second Style
Adapter for Mounting a Faceplate of a First Style to an Electrical Outlet Cavity of a Second Style
Adapter for Mounting a Faceplate of a First Style on to an Electrical Outlet Cavity of a Second Style
Patent:
6,927,340 →
Application:
10/451,544 →
Outlet with Analog Signal Adapter, a Method for Use Thereof and a Network Using Said Outlet
Outlet with Analog Signal Adapter, a Method for Use Thereof and a Network Using Said Outlet
Outlet with Analog Signal Adapter, a Method for Use Thereof and a Network Using Said Outlet
Outlet with Analog Signal Adapter, a Method for Use Thereof and a Network Using Said Outlet
Outlet with Analog Signal Adapter, a Method for Use Thereof and a Network Using Said Outlet
Local Area Network of Serial Intelligent Cells
Local Area Network of Serial Intelligent Cells
Local Area Network of Serial Intelligent Cells
Local Area Network of Serial Intelligent Cells
Local Area Network of Serial Intelligent Cells
Local Area Network of Serial Intelligent Cells
Local Area Network of Serial Intelligent Cells
Local Area Network of Serial Intelligent Cells
Local Area Network of Serial Intelligent Cells
Local Area Network of Serial Intelligent Cells
Local Area Network of Serial Intelligent Cells
Local Area Network of Serial Intelligent Cells
Local Area Network of Serial Intelligent Cells
Local Area Network of Serial Intelligent Cells
Local Area Network of Serial Intelligent Cells
Local Area Network of Serial Intelligent Cells
Local Area Network of Serial Intelligent Cells
Local Area Network of Serial Intellegent Cells
Local Area Network of Serial Intellegent Cells
Local Area Network of Serial Intelligent Cells
Patent:
6,480,510 →
Application:
09/123,486 →
Method and system for providing DC power on local telephone lines
Method and System for Providing Dc Power on Local Telephone Lines
Telephone System Having Multiple Sources and Accessories Therefor
Telephone System Having Multiple Distinct Sources and Accessories Therefor
Private Telephone Network Connected to More Than One Public Network
Modular Outlet
Modular Outlet
Modular Outlet
Modular Outlet
Modular Outlet
Modular Outlet
Addressable Outlet, and a Network Using the Same
Addressable Outlet, and a Network Using the Same
Outlet Add-on Module
Outlet Add-on Module
Outlet Add-on Module
Outlet Add-on Module
Outlet Add-on Module
Outlet Add-on Module
Device, Method and System for Estimating the Termination to a Wired Transmission-Line Based on Determination of Characteristic Impedance
Inertial Force Sensor and Electronic Device Using Same
Semiconductor Device
Synthesizer and Reception Device and Electronic Device Using the Same
Synthesizer and Reception Device
Electronic Device
Synthesizer, Synthesizer Module, and Reception Device and Electronic Device Using Same
Acceleration Sensor
Inertia Force Sensor
Angular Velocity Sensor
Angular Velocity Sensor Unit and Angular Velocity Sensor Diagnosing Device
Rotational-Rate Sensor
Sensor Signal Output Circuit
Electronic Apparatus and Method of Detecting Shock Given to the Electronic Apparatus
Angular Velocity Sensor, and Electronic Apparatus Using Same
Synthesizer and Reception Device Using the Same
Semiconductor Device and Method for Manufacturing the Same
Method for Manufacturing Electronic Component
Capacitive Sensor
Sensor Device
Temperature-Dependent Dram Self-Refresh Circuit
Methods for Programming and Reading Nand Flash Memory Device and Page Buffer Performing the Same
Method for Erasing Memory Cells in a Flash Memory Device Using a Positive Well Bias Voltage and a Negative Word Line Voltage
Method for Erasing Memory Cells in a Flash Memory Device Using a Positive Well Bias Voltage and a Negative Word Line Voltage
Method for Erasing Memory Cells in a Flash Memory Device Using a Positive Well Bias Voltage and a Negative Word Line Voltage
Word Line Driver in a Hierarchical nor Flash Memory
Temperature Detector in an Integrated Circuit
Temperature Detector in an Integrated Circuit
Sleepmode Activation in a Slave Device
Patent:
6,393,572 →
Application:
09/300,902 →
Direct Memory Access Execution Engine with Indirect Addressing of Circular Queues in Addition to Direct Memory Addressing
Patent:
6,463,059 →
Application:
09/205,480 →
Dispersion Tolerant Optical System and Method
Method of Making a Dynamic Random Access Memory Device Utilizing Chemical Mechanical Polishing
Patent:
6,271,124 →
Application:
09/395,291 →
Dynamic Random Access Memory Device and Method for Fabricating the Same
Patent:
5,990,510 →
Application:
09/212,053 →
Semiconductor memory device having operation delay function of column address strobe command, and buffer and signal transmission circuit which are applied to the semiconductor memory device
Multi-State Non-Volatile Semiconductor Memory Device
Sdram Having Posted Cas Function
Memory Cell Decoder Not Including a Charge Pump
Integrated Circuit Chip Having Anti-Moisture-Absorption Film at Edge Thereof and Method of Forming Anti-Moisture-Absorption Film
Integrated Circuit Chip Having Anti-Moisture-Absorption Film at Edge Thereof and Method of Forming Anti-Moisture-Absorption Film
Patent:
46,549 →
Application:
14/025,203 →
Semiconductor Memory Device
Trench Isolatoin Regions Having Trench Liners with Recessed Ends
Trench isolation structure, semiconductor device having the same, and trench isolation method
Patent:
6,331,469 →
Application:
09/684,822 →
Multilayer Passivation Process for Forming Air Gaps Within a Dielectric Between Interconnections
Data input circuit of semiconductor memory device
Patent:
6,324,119 →
Application:
09/557,619 →
Recessed Gate Electrode Mos Transistors Having a Substantially Uniform Channel Length Across a Width of the Recessed Gate Electrode and Methods of Forming Same
Semiconductor Device Having Metal Lines with Slits
Semiconductor Device Having No Cracks in One or More Layers Underlying a Metal Line Layer
Semiconductor Device Having Metal Lines with Slits
Semiconductor Device Having Metal Lines with Slits
Semiconductor Device Having No Cracks in One or More Layers Underlying a Metal Line Layer and Method of Manufacturing the Same
Semiconductor Device Having No Cracks in One or More Layers Underlying a Metal Line Layer and Method of Manufacturing the Same
Contact Structure of Semiconductor Memory Device for Reducing Contact Related Defect and Contact Resistance and Method for Forming the Same
Patent:
6,072,242 →
Application:
09/209,649 →
Devices for Controlling Temperature Indications in Integrated Circuits Using Adjustable Threshold Temperatures
Patent:
6,442,500 →
Application:
09/359,438 →
Methods of Fabricating Conductive Lines in Integrated Circuits Using Insulating Sidewall Spacers and Conductive Lines So Fabricated
Patent:
6,066,556 →
Application:
09/184,918 →
Semiconductor Device Having Triple-Well
Patent:
6,225,199 →
Application:
09/348,381 →
Method for Fabricating a Dram Cell Capacitor Including Etching Upper Conductive Layer with Etching Byproduct Forming a Etch Barrier on the Conductive Pattern
Patent:
6,238,970 →
Application:
09/343,353 →
Method of fabricating self-aligning stacked capacitor using electroplating method
Patent:
6,255,187 →
Application:
09/551,524 →
Trench Isolation Method for Semiconductor Integrated Circuit
Patent:
6,268,265 →
Application:
09/346,450 →
Planarization Method of Insulating Layer for Semiconductor Device
Patent:
6,423,639 →
Application:
09/603,202 →
Metallization Process for Manufacturing Semiconductor Devices
Patent:
6,335,284 →
Application:
09/386,360 →
Method for Fabricating a Semiconductor Memory Device and the Structure Thereof
Patent:
6,337,267 →
Application:
09/347,821 →
Method of fabricating floating gates in semiconductor device
Patent:
6,342,451 →
Application:
09/558,683 →
Method of Manufacturing a Capacitor Having Oxide Layers with Different Impurities and Method of Fabricating a Semiconductor Device Comprising the Same
Patent:
6,376,303 →
Application:
09/499,295 →
Method of Forming T-Shaped Isolation Layer, Method of Forming Elevated Salicide Source/Drain Region Using the Same, and Semiconductor Device Having T-Shaped Isolation Layer
Method of Forming T-Shaped Isolation Layer, Method of Forming Elevated Salicide Source/Drain Region Using the Same, and Semiconductor Device Having T-Shaped Isolation Layer
Patent:
6,383,877 →
Application:
09/573,268 →
Method for Fabricating a Capacitor of a Semiconductor Device and a Capacitor Made Thereby
Patent:
6,391,736 →
Application:
09/704,763 →
Non-Volatile Semiconductor Memory Device Capable of Reducing Read Time
Patent:
6,434,042 →
Application:
09/703,393 →
Nonvolatile Memory Devices Having Alternative Programming
Patent:
6,434,052 →
Application:
09/222,044 →
Trench Isolation Method for Semiconductor Integrated Circuit
Patent:
6,436,611 →
Application:
09/611,799 →
Semiconductor Memory Device Having a Plurality of Laser Fuses
Patent:
6,448,626 →
Application:
09/672,924 →
Semiconductor Memory Device with Redundancy Logic Cell and Repair Method
Methods of Forming Self-Aligned Contact Pads on Electrically Conductive Lines
Methods of Forming Self-Aligned Contact Pads on Electrically Conductive Lines
Patent:
6,268,252 →
Application:
09/442,523 →
Method of Repairing a Failed Wordline
Non-Volatile Semiconductor Memory Device
Patent:
6,466,478 →
Application:
09/847,115 →
Bit Line Sensing Control Circuit for a Semiconductor Memory Device and Layout of the Same
Method of Forming Interlevel Dielectric Layer of Semiconductor Device
Nonvolatile Semiconductor Memory Device and Manufacturing Method Thereof
Nonvolatile Semiconductor Memory Device and Manufacturing Method Thereof
Level-Shifting Reference Voltage Source Circuits and Methods
Semiconductor Memory Device Having a Memory Block with a Decreased Capacitance
Semiconductor Device Having Trench Isolation Structure and Method of Forming Same
Wafer Polishing Slurry and Chemical Mechanical Polishing (Cmp) Method Using the Same
Reference Voltage Generator
Method for Depositing a Tungsten Silicide Layer
Pattern Formation Method Using Two Alternating Phase Shift Masks
Method of Forming Semiconductor Device Having a Gaa Type Transistor
Nonvolatile Semiconductor Memory Device Having Changeable Spare Memory Address
Memory System Capable of Increasing Utilization Efficiency of Semiconductor Memory Device and Method of Refreshing the Semiconductor Memory Device
Transfer Circuit of Semiconductor Device and Structure Thereof
Capacitor of an Integrated Circuit Device and Method of Manufacturing the Same
Wiring Structure of Semiconductor Device
Wiring Structure of Semiconductor Device and Method for Manufacturing the Same
Patent:
6,355,515 →
Application:
09/359,243 →
Redundancy Circuit in Semiconductor Memory Device Having a Multiblock Structure
Delay Stage Insensitive to Operating Voltage and Delay Circuit Including the Same
Fixed Offset Digital-to-Analog Conversion Device and Method
Nonvolatile Semiconductor Memory Device with Scalable Two Transistor Memory Cells
Duty Cycle Correction Circuit of Delay Locked Loop and Delay Locked Loop Having the Duty Cycle Correction Circuit
Duty Cycle Correction Circuit of Delay Locked Loop and Delay Locked Loop Having the Duty Cycle Correction Circuit
Patent:
45,247 →
Application:
13/405,703 →
Input Signal Receiving Device of Semiconductor Memory Unit
Semiconductor Memory Device with Cylindrical Storage Electrode and Method of Manufacturing the Same
Etching Method in a Semiconductor Processing and Etching System for Performing the Same
Multi-Level High Voltage Generator
Flash Memory Device Capable of Preventing Program Disturbance According to Partial Programming
Non-Volatile Semiconductor Memory Device Having Shared Row Selection Circuit
Semiconductor Devices Having a Pocket Line and Methods of Fabricating the Same
Packet Addressing Programmable Dual Port Memory Devices and Related Methods
Duty Cycle Correction Circuit for Use in a Semiconductor Device
High Voltage Generator Circuit with Ripple Stabilization Function
Method of Forming an Interconnection Line in a Semiconductor Device
Sense Amplifier Circuit for Use in a Semiconductor Memory Device
Interface Circuit for Using in High-Speed Semiconductor Device and Interfacing Method
Tungsten layer formation method for semiconductor device and semiconductor device using the same
Patent:
6,404,054 →
Application:
09/609,927 →
Tungsten Layer Formation Method for Semiconductor Device and Semiconductor Device Using the Same
Patent:
6,579,794 →
Application:
09/357,126 →
Non-Volatile Semiconductor Memory Device Having Sense Amplifier with Increased Speed
Circuit and Method for Generating Wordline Voltage in Nonvolatile Semiconductor Memory Device
Trench Isolation Method
Patent:
6,255,194 →
Application:
09/324,919 →
Semiconductor Devices Having a Contact Plug and Fabrication Methods Thereof
Methods of Forming Iintegrated Circuit Devices Having a Metal-Insulator-Metal (Mim) Capacitor
Semiconductor Devices Having a Contact Plug and Fabrication Methods Thereof
Application:
13/593,655 →
Data Driving Circuit and Semiconductor Memory Device Having the Same
System for Transmitting Messages to Improved Stations, and Corresponding Processing
Patent:
6,697,379 →
Application:
09/312,486 →
Method and Apparatus for Connecting Network Segments
Patent:
6,483,852 →
Application:
09/210,456 →
Method and Apparatus for Optimizing Performance and Battery Life of Electronic Devices Based on System and Application Parameters
Patent:
7,111,179 →
Application:
10/268,914 →
Method and System for State-Dependent Admission Control and Routing of Multi-Rate Circuit-Switched Traffic
Patent:
6,366,559 →
Application:
09/092,732 →
Adaptive Layered Coding for Voice Over Wireless Ip Applications
Patent:
6,434,191 →
Application:
09/653,913 →
Method and Systems for Bandwidth Management in Packet Data Networks
Method and System for Design and Routing in Transparent Optical Networks
Dynamic Traffic Rearrangement and Restoration for Mpls Networks with Differentiated Services Capabilities
Sense Amplifier Driving Device
Patent:
6,144,230 →
Application:
09/317,113 →
Plural Memory Banks Memory Device That Can Simultaneously Read from or Write to All of the Memory Banks During Testing
Patent:
6,198,667 →
Application:
09/290,399 →
Apparatus and Method for Performing Data Read Operation in Ddr Sdram
Patent:
6,201,760 →
Application:
09/461,718 →
Method for Fabricating Contact Pad for Semiconductor Device
Patent:
6,297,091 →
Application:
09/397,136 →
A Semiconductor Memory Array Layout
Patent:
6,329,678 →
Application:
09/451,852 →
Method for fabricating a semiconductor memory device
Patent:
6,350,650 →
Application:
09/710,958 →
Data Bus Line Control Circuit
Patent:
44,051 →
Application:
13/335,207 →
Semiconductor Memory Device Having a Plurality of Banks Sharing a Column Control Unit
Analog Mixed Digital Dll
Patent:
6,392,456 →
Application:
09/427,272 →
Method of Forming a Contact Plug for a Semiconductor Device
Patent:
45,232 →
Application:
13/568,920 →
Gate Structure with High K Dielectric
Method for Making High K Dielectric Gate for Semiconductor Device
Column Transistor for Semiconductor Devices
Delay Locked Loop for Use in Semiconductor Memory Device
Method of Forming Contact Holes in Semiconductor Devices and Method of Forming Capacitors Using the Same
Method of Forming Dual-Metal Gates in Semiconductor Device
Circuit for Generating Internal Address in Semiconductor Memory Device
Semiconductor Device and Method for Fabricating the Same
Damascene Capacitor Formed in Metal Interconnection Layer
Semiconductor Memory Device with Modified Global Input/Output Scheme
Delay Locked Loop and Locking Method Thereof
Patent:
6,943,602 →
Application:
11/026,970 →
Semiconductor Memory Device Having Row Path Control Circuit and Operating Method Thereof
Semiconductor Memory Device
Method of Forming a Metal Gate in a Semiconductor Device Using Atomic Layer Deposition Process
On Die Termination Mode Transfer Circuit in Semiconductor Memory Device and Its Method
Clock Control Device for Toggling an Internal Clock of a Synchronous Dram for Reduced Power Consumption
Patent:
44,590 →
Application:
13/369,988 →
Method for Fabricating Semiconductor Device Having Capacitor
Semiconductor Memory Device Sharing a Data Line Sense Amplifier and a Write Driver in Order to Reduce a Chip Size
Method of Manufacturing Semiconductor Device with Recess and Fin Structure
Semiconductor Device with Recess and Fin Structure
Method for Fabricating a Semiconductor Device
Method for Manufacturing a Transistor of a Semiconductor Memory Device
Transistor of Semiconductor Memory Device
Method for Manufacturing a Transistor of a Semiconductor Memory Device
Patent:
44,532 →
Application:
13/586,272 →
Method for Manufacturing a Transistor of a Semiconductor Memory Device
Five Channel Fin Transistor and Method for Fabricating the Same
Method for Forming Storage Node of Capacitor in Semiconductor Device
Method for Forming Storage Node of Capacitor in Semiconductor Device
Synchronous Dynamic Random Access Memory in a Semiconductor Memory Device
Patent:
6,064,619 →
Application:
09/106,308 →
Method for Manufacturing a Capacitor of a Semiconductor Device
Patent:
6,066,540 →
Application:
09/143,096 →
Delay Locked Loop with Delay Control Unit for Noise Elimination
Semiconductor Memory Device and Driving Method Thereof
Semiconductor Memory Device and Driving Method Thereof
Patent:
44,632 →
Application:
13/538,130 →
Semiconductor Memory Device and Driving Method Thereof
Adjusable Substrate Voltage Applying Circuit of a Semiconductor Device
Patent:
6,150,870 →
Application:
09/195,202 →
Delay Locked Loop Device of the Semiconductor Circuit
Patent:
6,154,073 →
Application:
09/196,121 →
Method of Forming Capacitor of Semiconductor Device
Patent:
6,207,496 →
Application:
09/362,210 →
Semiconductor Device Having Capacitor and Method of Fabricating the Same
Patent:
6,242,316 →
Application:
09/457,340 →
Semiconductor Device Having Capacitor
Patent:
6,034,392 →
Application:
09/151,601 →
Circuit for Standby Current Reduction
Patent:
6,288,586 →
Application:
09/243,469 →
Semiconductor Device Having Improved on-Off Current Characteristics
Patent:
6,291,865 →
Application:
09/217,574 →
Method for forming multi-layer interconnection of a semiconductor device
Patent:
6,313,029 →
Application:
09/606,874 →
Method for forming a gate electrode on a semiconductor substrate
Patent:
6,306,743 →
Application:
09/798,942 →
Method of Manufacturing Semiconductor Devices with Titanium Aluminum Nitride Work Function
Capacitor for Semiconductor Memory Device
Patent:
6,507,062 →
Application:
10/013,402 →
Capacitor for Semiconductor Memory Device and Fabrication Method Thereof
Patent:
6,342,425 →
Application:
09/417,775 →
Circuit and Method for Controlling Buffers in Semiconductor Memory Device
Duty Correction Circuit and a Method of Correcting a Duty
Patent:
6,525,581 →
Application:
10/033,989 →
Semiconductor Memory Device Having Capacitor Structure Formed in Proximity to Corresponding Transistor
Self Refresh Circuit for Semiconductor Memory Device
Duty Cycle Correction Circuit
Low Power Semiconductor Memory Device Having a Normal Mode and a Partial Array Self Refresh Mode
Method of Manufacturing a Contact Plug for a Semiconductor Device
Apparatus and Method of Compensating for Phase Delay in Semiconductor Device
High Voltage Supply Circuit and a Method of Supplying High Voltage
Data Output Control Circuit
Write Circuit of Double Data Rate Synchronous Dram
Semiconductor Memory Device for Controlling Write Recovery Time
Patent:
44,218 →
Application:
13/335,234 →
Semiconductor Memory Device for Controlling Write Recovery Time
Method of Inhibiting Degradation of Gate Oxide Film
Memory Apparatus Having Multi-Port Architecture for Supporting Multi Processor
Clock Signal Generation Apparatus for Use in Semiconductor Memory Device and Its Method
Patent:
44,230 →
Application:
13/367,023 →
Clock Signal Generation Apparatus for Use in Semiconductor Memory Device and Its Method
Memory Chip Architecture Having Non-Rectangular Memory Banks and Method for Arranging Memory Banks
Pmos Transistor of Semiconductor Device, Semiconductor Device Comprising the Same, and Method for Manufacturing the Same
Semiconductor Memory Device
Patent:
45,036 →
Application:
13/779,097 →
Multi-Chip Package
Patent:
6,121,682 →
Application:
09/469,131 →
Method of Preventing Bowing in a via Formation Process
Patent:
6,124,208 →
Application:
09/186,354 →
Method of Preventing Bowing in a via Formation Process
Application:
14/025,073 →
Delay Locked Loop Using Bidirectional Delay
Patent:
6,239,641 →
Application:
09/476,380 →
Phase Splitter
Patent:
6,292,042 →
Application:
09/295,403 →
Method for Fabricating Semiconductor Device
Method for Forming Gate Oxide Film in Semiconductor Device
Patent:
6,355,579 →
Application:
09/442,736 →
Semiconductor Device and Method of Fabricating the Same
Stackable Ball Grid Array Semiconductor Package and Fabrication Method Thereof
Stackable Ball Grid Array Semiconductor Package and Fabrication Method Thereof
Patent:
6,291,259 →
Application:
09/239,152 →
Mosfet Device Fabrication Method Capable of Allowing Application of Self-Aligned Contact Process While Maintaining Metal Gate to Have Uniform Thickness
Delay Locked Loop Incorporating a Ring Type Delay and Counting Elements
Method for Fabricating Semiconductor Device Having a Capacitor
Semiconductor Memory Device Incorporating Therein Ruthenium Electrode and Method for the Manufacture Thereof
Method of Forming a Metal Wiring in a Semiconductor Device with Copper Seed
Register Controlled Dll Reducing Current Consumption
Method for Forming Wire in Semiconductor Device
Apparatus and Method for Operation of Multi-Bank Semiconductor Memory Device with an Up/Down Counter
Cmos of Semiconductor Device and Method for Manufacturing the Same
Semiconductor Device Having a Metal Insulator Metal Capacitor
Method for Fabricating Metal-Oxide Semiconductor Transistor
Semiconductor Chip Package and Method of Fabricating Same
Patent:
6,458,627 →
Application:
09/415,267 →
Method of Fabricating Dielectric Layer
Method for Forming Conductive Line of Semiconductor Device
Semiconductor Memory Device for Low Power System
Semiconductor Memory Device for Simultaneously Testing Blocks of Cells
Voltage Regulating Circuit and Method of Regulating Voltage
Method for Manufacturing Semiconductor Device
Method for Fabricating Semiconductor Device
Semiconductor Device and Method for Fabricating a Semiconductor Device
Method of Manufacturing Semiconductor Device
Self Refresh Oscillator and Oscillation Signal Generation Method of the Same
On-Die Termination Circuit and the Driving Method Thereof
Patent:
45,246 →
Application:
13/706,541 →
Impurity Ion Segregation Precluding Layer, Fabrication Method Thereof, Isolation Structure for Semiconductor Device Using the Impurity Ion Segregation Precluding Layer and Fabricating Method Thereof
Patent:
6,337,256 →
Application:
09/441,206 →
Method of Forming a Gate Electrode in a Semiconductor Device
Patent:
6,514,826 →
Application:
09/721,636 →
Method of Manufacturing Semiconductor Devices
Demonstration Control Adjunct Device for Printers
Delay Locking High Speed Clock Synchronization Method And Circuit
Patent:
6,310,822 →
Application:
09/498,739 →
Internal Power Management Scheme for a Memory Chip in Deep Power Down Mode
Internal Power Management Scheme for a Memory Chip in Deep Power Down Mode
Method and Test Structure for Low-Temperature Integration of High Dielectric Constant Gate Dielectrics into Self-Aligned Semiconductor Devices
Patent:
6,210,999 →
Application:
09/205,047 →
Gradated Barrier Layer in Integrated Circuit Interconnects
Patent:
6,462,416 →
Application:
09/905,469 →
Method of Forming Semiconductor Devices with Differently Composed Metal-Based Gate Electrodes
Patent:
6,518,154 →
Application:
09/813,310 →
Fabrication of P-Channel Field Effect Transistor with Minimized Degradation of Metal Oxide Gate
Patent:
6,365,450 →
Application:
09/809,706 →
Dual Damascene Arrangement for Metal Interconnection with Oxide Dielectric Layer and Low K Dielectric Constant Layer
Patent:
6,380,091 →
Application:
09/238,050 →
Transistor Having Enhanced Metal Silicide and a Self-Aligned Gate Electrode
Patent:
6,410,967 →
Application:
09/173,273 →
Semiconductor Device with Variable Composition Low-K Inter-Layer Dielectric and Method of Making
Patent:
6,518,646 →
Application:
09/819,615 →
Recessed Source Drains to Reduce Fringing Capacitance
Patent:
6,531,347 →
Application:
09/776,713 →
Double Gate Semiconductor Device Having Separate Gates
Patent:
6,611,029 →
Application:
10/290,158 →
Narrow Fins by Oxidation in Double-Gate Finfet
Patent:
6,812,119 →
Application:
10/614,052 →
Method of Manufacturing Semiconductor Device Comprising Silicon-Rich Tasin Metal Gate Electrode
Patent:
6,861,350 →
Application:
10/464,508 →
Method of Fabricating a Semiconductor Device Having a Mos Transistor with a High Dielectric Constant Material
Patent:
6,686,248 →
Application:
09/825,658 →
Nickel Silicide Process Using Non-Reactive Spacer
Patent:
6,724,051 →
Application:
09/679,877 →
Narrow Body Raised Source/Drain Metal Gate Mosfet
Patent:
7,034,361 →
Application:
10/653,234 →
Method for Lateral Trimming of Spacers
Patent:
6,821,713 →
Application:
10/085,242 →
Technique for Forming Recessed Sidewall Spacers for a Polysilicon Line
Slotted Trench Dual Inlaid Structure and Method of Forming Thereof
Patent:
6,524,947 →
Application:
09/774,800 →
Methods for Improving Carrier Mobility of Pmos and Nmos Devices
Patent:
6,573,172 →
Application:
10/244,439 →
Providing Stress Uniformity in a Semiconductor Device
Conductor Bump Method and Apparatus
Conductor Bump Method and Apparatus
Reducing Transistor Junction Capacitance by Recessing Drain and Source Regions
Reducing Transistor Junction Capacitance by Recessing Drain and Source Regions
Technique for Providing Stress Sources in Transistors in Close Proximity to a Channel Region by Recessing Drain and Source Regions
Technique for Providing Stress Sources in Transistors in Close Proximity to a Channel Region by Recessing Drain and Source Regions
Contacts and Vias of a Semiconductor Device Formed by a Hard Mask and Double Exposure
Aluminum Disposable Spacer to Reduce Mask Count in Cmos Transistor Formation
Patent:
6,265,253 →
Application:
09/305,098 →
Phosphoric Acid Process for Removal of Contact Barc Layer
Patent:
6,127,259 →
Application:
09/372,443 →
Method of fabricating a deep source/drain
Patent:
6,358,803 →
Application:
09/489,369 →
Sacrificial Tin Arc Layer for Increased Pad Etch Throughput
Patent:
7,071,101 →
Application:
09/208,325 →
Method of Strengthening Photoresist to Prevent Pattern Collapse
Patent:
6,635,409 →
Application:
09/902,568 →
Method of Controlling the Chemical Mechanical Polishing of Stacked Layers Having a Surface Topology
Slurry-Less Polishing for Removal of Excess Interconnect Material During Fabrication of a Silicon Integrated Circuit
Patent:
7,141,502 →
Application:
10/673,597 →
End-Of-Range Defect Minimization in Semiconductor Device
Patent:
7,091,097 →
Application:
10/933,424 →
Methods for Fabricating an Integrated Circuit
Soi Semiconductor Components and Methods for Their Fabrication
Soi Semiconductor Components and Methods for Their Fabrication
Method of Forming a Semiconductor Structure Comprising an Implantation of Ions of a Non-Doping Element
Anneal Hillock Suppression Method in Integrated Circuit Interconnects
Patent:
6,500,754 →
Application:
09/999,661 →
Hybrid Wireless Short Range Payment System and Method
Synthetic Barcode Payment System and Method
Patent:
9,239,979 →
Application:
14/598,219 →
Non-Volatile Memory Devices and Control and Operation Thereof
Non-Volatile Memory Devices and Control and Operation Thereof
Non-Volatile Memory Devices and Control and Operation Thereof
Non-Volatile Memory Devices and Control and Operation Thereof
Contiguous Block Addressing Scheme
Contiguous Block Addressing Scheme
Contiguous Block Addressing Scheme
Contiguous Block Addressing Scheme
Semiconductor Memory Having Segmented Row Repair
Semiconductor memory having segmented row repair
Patent:
6,314,030 →
Application:
09/594,442 →
Circuit, System and Method for Selectively Turning Off Internal Clock Drivers
Circuit, System and Method for Selectively Turning Off Internal Clock Drivers
Circuit, System and Method for Selectively Turning Off Internal Clock Drivers
Circuit, System and Method for Selectively Turning Off Internal Clock Drivers
Circuit, System and Method for Selectively Turning Off Internal Clock Drivers
Erase Block Architecture for Non-Volatile Memory
Erase Block Architecture for Non-Volatile Memory
Patent:
6,587,383 →
Application:
10/100,856 →
Synchronous Dram with Selectable Internal Prefetch Size
Synchronous Dram with Selectable Internal Prefetch Size
Synchronous Dram with Selectable Internal Prefetch Size
Method for Repairing a Semiconductor Memory
Memory Device and Method for Repairing a Semiconductor Memory
Device and Method for Repairing a Semiconductor Memory
Patent:
6,199,177 →
Application:
09/143,283 →
Metal Local Interconnect Self-Aligned Source Flash Cell
Data Path Having Grounded Precharge Operation and Test Compression Capability
Data Path Having Grounded Precharge Operation and Test Compression Capability
Flash Memory Device with Improved Programming Performance
Flash Memory Device with Improved Programming Performance
Flash Memory Device with Improved Programming Performance
Capacitor Structures
Method of Forming Dram Trench Capacitor with Metal Layer Over Hemispherical Grain Polysilicon
Apparatus and Method for Increasing Test Flexibility of a Memory Device
Patent:
6,459,635 →
Application:
09/703,360 →
Apparatus and Method for Increasing Test Flexibility of a Memory Device
Patent:
6,141,276 →
Application:
09/389,680 →
Reduced Area Sense Amplifier Isolation Layout in a Dynamic Ram Architecture
Patent:
6,480,407 →
Application:
08/519,504 →
Capacitor Constructions
Methods of Forming Capacitors
Graded Layer for Use in Semiconductor Circuits and Method for Making Same
Graded Layer for Use in Semiconductor Circuits and Method for Making Same
Graded Layer for Use in Semiconductor Circuits and Method for Making Same
Patent:
6,271,590 →
Application:
09/138,811 →
Methods and Apparatus for Duty Cycle Control
Sequential Pulse Deposition
Sequential Pulse Deposition
Semiconductor Circuit Design Methods, Semiconductor Processing Methods and Integrated Circuitry
A Semiconductor Circuit Design Method for Employing Spacing Constraints and Circuits Thereof
Patent:
6,223,331 →
Application:
09/126,877 →
Surface cleaning apparatus
Patent:
6,269,511 →
Application:
09/679,806 →
Surface Cleaning Apparatus and Method
Patent:
6,273,100 →
Application:
09/141,384 →
Rhodium-Rich Oxygen Barriers
Method and Apparatus for Inspecting Wafers
Selective Method to Form Roughened Silicon
Patent:
6,355,536 →
Application:
09/093,217 →
Barrier-Metal-Free Copper Damascene Technology Using Atomic Hydrogen Enhanced Reflow
Barrier-Metal-Free Copper Damascene Technology Using Atomic Hydrogen Enhanced Reflow
Methods for Forming and Integrated Circuit Structures Containing Ruthenium and Tungsten Containing Layers
Methods for Forming and Integrated Circuit Structures Containing Ruthenium and Tungsten Containing Layers
Patent:
7,253,076 →
Application:
09/590,795 →
A Vertical Transistor Having a Vertical Gate Structure Having a Top or Upper Surface Defining a Facet Formed Between a Vertical Source and a Vertical Drain.
Method for Forming Raised Structures by Controlled Selective Epitaxial Growth of Facet Using Spacer
Diffusion Barrier Layers and Methods of Forming Same
Patent:
6,323,081 →
Application:
09/146,866 →
Methods and Solutions for Cleaning Polished Aluminum-Containing Layers, Methods for Making Metallization Structures, and the Structures Resulting from These Methods
Methods and Solutions for Cleaning Polished Aluminum-Containing Layers, Methods for Making Metallization Structures, and the Structures Resulting from These Methods
Patent:
6,265,781 →
Application:
09/153,053 →
Double Layer Electrode and Barrier System on Hemispherical Grain Silicon for Use with High Dielectric Constant Materials and Methods for Fabricating the Same
Double Layer Electrode and Barrier System on Hemispherical Grain Silicon for Use with High Dielectric Constant Materials and Methods for Fabricating the Same
Double Layer Electrode and Barrier System on Hemispherical Grain Silicon for Use with High Dielectric Constant Materials and Methods for Fabricating the Same
Patent:
6,281,543 →
Application:
09/386,833 →
Gapped-Plate Capacitor
Patent:
6,498,363 →
Application:
09/652,837 →
Gapped-Plate Capacitor
Gapped-Plate Capacitor
Gapped-Plate Capacitor
Gapped-Plate Capacitor
Patent:
6,316,326 →
Application:
09/229,857 →
Gapped-Plate Capacitor
Patent:
6,018,175 →
Application:
09/148,032 →
Aluminum-Beryllium Alloys for Air Bridges
Patent:
6,509,590 →
Application:
09/119,355 →
Deadhesion Method and Mechanism for Wafer Processing
Deadhesion Method and Mechanism for Wafer Processing
Patent:
6,316,363 →
Application:
09/387,429 →
Chemical Treatment of Semiconductor Substrates
Patent:
6,395,647 →
Application:
09/388,570 →
Capacitor Electrode for Integrating High K Materials
Capacitor Electrode for Integrating High K Materials
Patent:
6,750,500 →
Application:
09/225,887 →
Methods of Forming Semiconductor Circuit Constructions and Capacitor Constructions
Semiconductor Circuit Constructions, Capacitor Constructions, and Methods of Forming Semiconductor Circuit Constructions and Capacitor Constructions
Patent:
6,555,863 →
Application:
09/566,673 →
Semiconductor Circuit Constructions,Capacitor Constructions, and Methods of Forming Semiconductor Circuit Constructions and Capacitor Constructions
Methods of Forming Semiconductor Circuit Constructions and Capacitor Constructions
Methods of Forming Materials Comprising Tungsten and Nitrogen, and Methods of Forming Capacitors
Methods of Forming Materials Comprising Tungsten and Nitrogen
Isolation and/or Removal of Ionic Contaminants from Planarization Fluid Compositions Using Macrocyclic Polyethers
Patent:
6,458,290 →
Application:
09/642,682 →
Isolation and/or Removal of Ionic Contaminants from Planarization Fluid Compositions Using Macrocyclic Polyethers and Methods of Using Such Compositions
Patent:
6,468,909 →
Application:
09/146,299 →
Shared Length Cell for Improved Capacitance
Shared Length Cell for Improved Capacitance
Patent:
6,180,452 →
Application:
09/436,213 →
Shared Length Cell for Improved Capacitance
Patent:
6,025,624 →
Application:
09/099,765 →
System and Method for Selectively Increasing Surface Temperature of an Object
Organic Field Ionization Source
Organic Field Ionization Source
Patent:
6,265,722 →
Application:
09/386,976 →
Reduction of Surface Roughness During Chemical Mechanical Planarization(Cmp)
Patent:
6,426,295 →
Application:
09/584,468 →
Reduction of Surface Roughness During Chemical Mechanical Planarization (Cmp)
Composition and Method of Formation and Use Therefor in Chemical-Mechanical Polishing
Composition and Method of Formation and Use Therefor in Chemical-Mechanical Polishing
Patent:
6,409,936 →
Application:
09/252,022 →
Integrated Circuit Capacitor Structures
Methods of Forming Capacitors and Resultant Capacitor Structures
Methods of Forming Capacitors and Resultant Capacitor Structures
Patent:
6,403,442 →
Application:
09/389,533 →
Solutions of Metal-Comprising Materials, Methods of Forming Metal-Comprising Layers, Methods of Storing Metal-Comprising Materials, and Methods of Forming Capacitors
Solutions of Metal-Comprising Materials
Methods of Making Semiconductor Devices
Patent:
6,319,832 →
Application:
09/253,307 →
Method of Forming High Aspect Ratio Structures for Seminconductor Devices
Patent:
6,204,143 →
Application:
09/293,635 →
Method for Improved Processing and Etchback of a Container Capacitor
Method for Improved Processing and Etchback of a Container Capacitor
Patent:
6,319,789 →
Application:
09/235,752 →
Method of Depositing a Nitrogen Enriched Metal Layer, Method of Forming a Silicide Contact to a Silicon Comprising Substrate, Method of Forming a Metal Source Layer in an Integrated Circuit, Method of Analyzing Impact of Operating Parameter Changes for a Plasma Depositio
Patent:
6,365,507 →
Application:
09/260,237 →
Method of Forming Low Dielectric Silicon Oxynitride Spacer Films Highly Selective to Etchants
Patent:
6,518,626 →
Application:
09/507,463 →
Capacitor and method of forming a capacitor
Patent:
6,313,496 →
Application:
09/654,930 →
Method of Forming a Capacitor
Apparatus and Method for Feature Edge Detection in Semiconductor Processing
Apparatus and Method for Feature Edge Detection in Semiconductor Processing
Patent:
6,624,897 →
Application:
09/292,396 →
Methods of Forming Semiconductor Constructions
Methods of Forming Nitrogen-Containing Masses, Silicon Nitride Layers, and Capacitor Constructions
Integrated Circuitry and Dram Circuitry
Patent:
6,570,204 →
Application:
09/654,297 →
Method of Forming a Pair of Capacitors Having a Common Capacitor Electrode, Method of Forming Dram Circuitry, Integrated Circuitry and Dram Circuitry
Patent:
6,277,687 →
Application:
09/323,440 →
Stereolithographic Method for Applying Materials to Electronic Component Substrates and Resulting Structures
Patent:
6,524,346 →
Application:
09/259,143 →
Method for Producing Water for Use in Manufacturing Semiconductors
Patent:
6,440,382 →
Application:
09/387,119 →
Method of Fabricating an SRRUO3 Film
Method of fabricating an SrRuO3 Film
Patent:
6,342,445 →
Application:
09/571,718 →
Method of Selective Oxidation in Semiconductor Manufacture
Patent:
6,458,714 →
Application:
09/721,839 →
Platinum-Rhodium Stack as an Oxygen Barrier
Semiconductor Processing Methods
Localized Array Threshold Voltage Implant to Enhance Charge Storage Within Dram Memory Cells
Sensor Devices, Methods and Systems for Detecting Gas Phase Materials
Patent:
6,479,297 →
Application:
09/652,634 →
Integrated Circuit Devices Having Contact and Container Structures
Methods for Forming Contact and Container Structures, and Integrated Circuit Devices Therefrom
Patent:
6,383,868 →
Application:
09/653,501 →
Mixed Composition Interface Layer and Method of Forming
Patent:
43,025 →
Application:
12/566,533 →
Dram Cell Constructions
Methods of Forming Dram Cells
Dram Cell Constructions
Dram Cell Constructions, and Methods of Forming Dram Cells
Patent:
6,429,070 →
Application:
09/651,484 →
Method of Forming a Capacitor Container Electrode and Method of Patterning a Metal Layer by Selectively Silicizing the Electrode or Metal Layer and Removing the Silicized Portion
Patent:
6,372,574 →
Application:
09/586,321 →
Reduced Aspect Ratio Digit Line Contact Process Flow Used During the Formation of a Semiconductor Device
Integrated Decoupling Capacitors
A Capacitor Having Rusixoy-Containing Adhesion Layers
Rusixoy-Containing Adhesion Layers
Process for Fabricating Rusixoy-Containing Adhesion Layers
Patent:
6,461,909 →
Application:
09/651,859 →
Cvd of Ptrh with Good Adhesion and Morphology
Method and Apparatus for Controlling Radiation Beam Intensity Directed to Microlithograhic Substrates
Nanotube Semiconductor Devices and Methods for Making the Same
Patent:
6,515,325 →
Application:
10/092,829 →
Microlithographic Mask Structures and Method of Fabrication
Reducing Asymmetrically Deposited Film Induced Registration Error
Reducing Asymmetrically Deposited Film Induced Registration Error
Apparatus and System for Removing Photoresist Through the Use of Hot Deionized Water Bath, Water Vapor and Ozone Gas
Removal of Photoresist Through the Use of Hot Deionized Water Bath, Water Vapor and Ozone Gas
Patent:
6,558,477 →
Application:
09/688,757 →
Method of Forming Memory Circuitry and Method of Forming Memory Circuitry Comprising a Buried Bit Line Array of Memory Cells
Patent:
6,376,380 →
Application:
09/652,601 →
Method and Apparatus for the Fabrication of Ferroelectric Films
Dielectric Material Forming Methods and Enhanced Dielectric Materials
Dielectric Material Forming Methods and Enhanced Dielectric Materials
Methods for preparing ruthenium oxide films
Patent:
6,281,125 →
Application:
09/573,034 →
Solvated Ruthenium Precursors for Direct Liquid Injection of Ruthenium and Ruthenium Oxide
Solvated Ruthenium Precursors for Direct Liquid Injection Ofruthenium and Ruthenium Oxide
Methods for Preparing Ruthenium Metal Films
Patent:
6,074,945 →
Application:
09/140,878 →
Methods for Preparing Ruthenium Oxide Films
Patent:
6,133,159 →
Application:
09/140,932 →
Method for Fabricating Complex Three-Dimensional Structures on the Submicrometric Scale by Combined Lithography of Two Resists
Semiconductor Chip, Set of Semiconductor Chips and Multichip Module
Integrated Circuit Device and Method for Forming the Same
Integrated Circuit Device and Method for Forming the Same
Integrated Circuit Device and Method for Forming the Same
Integrated Circuit Device and Method for Forming the Same
Integrated Circuit Device and Method for Forming the Same
Semiconductor Chip and Multi-Chip Module
Semiconductor Integrated Circuit
Semiconductor Device for Reducing Parasitic Capacitance Produced in the Vicinity of a Transistor Located Within the Semiconductor Device
Solid-State Image Sensor and Method of Manufacturing Thereof
Method for Fabricating Nonvolatile Semiconductor Memory Device
Solid State Imaging Device and Method for Manufacturing the Same
Semiconductor Integrated Circuit and Design Method Thereof
Semiconductor Integrated Circuit and Design Method Thereof
Semiconductor Integrated Circuit
Semiconductor Integrated Circuit
Solid State Imaging Device in Which a Plurality of Imaging Pixels Are Arranged Two-Dimensionally, and a Manufacturing Method for the Solid State Imaging Device
Mos Solid-State Image Pickup Device
Semiconductor Device and Method for Fabricating the Same
Electronic Equipment System and Semiconductor Integrated Circuit Controller
Manufacturing Method of Solid-State Image Sensor
Manufacturing Method of Solid-State Image Sensor
Patent:
47,208 →
Application:
15/582,014 →
Pinned Photodiode for a Cmos Image Sensor and Fabricating Method Thereof
Pinned Photodiode for a Cmos Image Sensor and Fabricating Method Thereof
Cmos Image Sensor
Cmos Image Sensor
Cmos Image Sensor and Method for Fabricating the Same
Cmos Image Sensor and Method for Fabricating the Same
Cmos Image Sensor and Method for Fabricating the Same
Cmos Image Sensor and Method for Manufacturing the Same
Cmos Image Sensor Having Impurity Diffusion Region Separated from Isolation Region
Cmos Image Sensor and Method for Manufacturing the Same
Image Sensor and Method for Manufacturing the Same
Cmos Image Sensor and Method of Fabricating the Same
Image Sensor and Fabricating Method Thereof
Image Sensor and Method for Manufacturing the Same
Cmos Image Sensor and Method for Manufacturing the Same
Cmos Image Sensor and Method for Manufacturing the Same
Cmos Image Sensor and Manufacturing Method Thereof
Color Filter of Image Sensor, Image Sensor, and Method for Manufacturing the Image Sensor
Color Filter of Image Sensor, Image Sensor, and Method for Manufacturing the Image Sensor
Image Sensor Having Dielectric Layer Which Allows First Impurity Region of Photodiode to Be Isolated from Contact Plug and Second Impurity Region of the Photodiode to Contact the Contact Plug
Image Sensor and Method for Manufacturing the Same
Image Sensor
Image Sensor
Image Sensor and Method for Fabricating the Same
Cmos Image Sensor and Method for Fabricating the Same
Cmos Image Sensor and Method for Manufacturing the Same
Image Sensor and Method for Manufacturing the Same
Image Sensor and Methods of Driving and Fabricating the Same
Image Sensor
Limiting Power State Changes to a Processor of a Computer Device
Retiring Early-Completion Instructions to Improve Computer Operation Throughput
System and Method Utilizing on-Chip Voltage Monitoring to Manage Power Consumption
Multiple frequency switching power supply and methods to operate a switching power supply
Patent:
6,294,904 →
Application:
09/656,669 →
Multiple Frequency Switching Power Supply and Methods to Operate a Switching Power Supply
Patent:
6,127,816 →
Application:
09/368,401 →
Opportunistic Transmission of Portably Stored Digital Data
A Method of Protecting User Process Data in a Secure Platform Inaccessible to the Operating System and Other Tasks on Top of the Secure Platform
Managing Latencies in Accessing Memory of Computer Systems
Memory Table and Memory Manager for Use in Managing Memory
Method and System for Creating Secure Address Space Using Hardware Memory Router
Adapting Vlsi Clocking to Short Term Voltage Transients
Driver Circuit Connected to Pulse Shaping Circuitry
Driver Circuit Connected to a Switched Capacitor and Method of Operating Same
System and method for enabling/disabling sram banks for memory access
Patent:
6,285,579 →
Application:
09/505,561 →
System for Enabling a Receiver for Only a Fix Amount of Time and Disabling the Receiver Thereafter
Patent:
6,668,329 →
Application:
09/392,424 →
Contention Based Logic Gate Driving a Latch and Driven by Pulsed Clock
Patent:
6,265,897 →
Application:
09/466,493 →
Scalable System Control Unit for Distributed Shared Memory Multi-Processor Systems
Patent:
6,378,029 →
Application:
09/295,668 →
Scalable, Re-Configurable Crossbar Switch Architecture for Multi-Processor System Interconnection Networks
Backup Redundant Routing System Crossbar Switch Architecture for Multi-Processor System Interconnection Networks
Patent:
6,263,415 →
Application:
09/296,038 →
Redundant Data Storage Systems and Methods of Operating a Redundant Data Storage System
Method and System for Directly Interconnecting Storage Devices to Controller Cards Within a Highly Available Storage System
Method, Computer System and Computer Program Product for Processing Extensible Markup Language Streams
A System and Method for Managing Power Consumption for a Plurality of Processors Based on a Supply Voltage to Each Processor, Temperature, Total Power Consumption and Individual Processor Power Consumption
Method and Structure for External Control of Esd Protection in Electronic Circuits
System Workload Characterization
Patent:
7,203,621 →
Application:
10/164,534 →
Method and Apparatus for Saving Power in Dynamic Circuits
Patent:
6,624,686 →
Application:
10/205,831 →
System and Method for Using a Using Vendor-Long Descriptor in Acpi for the Chipset Registers
Programmable Clock Synchronizer
A Controller Arrangement for Synchronizer Data Transfer Between a Core Clock Domain and Bus Clock Domain Each Having Its Own Individual Synchronizing Controller
System and Method for Synchronizing Multiple Synchronizer Controllers
System and Method for Maintaining a Stable Synchronization State in a Programmable Clock Synchronizer
System and Method for Compensating for Skew Between a First Clock Signal and a Second Clock Signal
Phase Detector for a Programmable Clock Synchronizer
Phase Detection in a Sync Pulse Generator
Phase-Locked Loop Control Circuit
Method and Device for Circuit Control
Systems and Methods for Generating a Current
Distributed Multiplexing Circuit with Built-in Repeater
Output Buffer Slew Rate Control Using Clock Signal
Apparatus and Method of Tuning a Digitally Controlled Input/Output Driver
System and Method to Mitigate Voltage Fluctuations
Register-Based De-Skew System and Method for a Source Synchronous Receiver
Reset Scheme for I/O Pads in a Source Synchronous System
Receiver and Method for Mitigating Temporary Logic Transitions
Computer System Having Security Features for Authenticating Different Components
Patent:
6,625,729 →
Application:
09/540,811 →
Data Redundancy in a Hot Pluggable, Large Symmetric Multi-Processor System
Conditional Clock Gate That Reduces Data Dependent Loading on a Clock Network
Method and Apparatus for Preserving the Integrity of a Management Subsystem Environment
System and Method for Multi-Destination Merge in a Storage Area Network
Multi-Controller Write Operations
High Performance Multi-Controller Processing
Method and Apparatus for Supporting Heterogeneous Memory in Computer Systems
Method and Apparatus for Supporting Heterogeneous Memory in Computer Systems
Patent:
6,260,127 →
Application:
09/114,426 →
Read Around Speculative Load
Patent:
6,567,901 →
Application:
09/514,981 →
Method and Apparatus for Disabling a Processor in a Multiprocessor Computer
Patent:
6,496,881 →
Application:
09/266,506 →
Memory Controller with Temperature Sensors
Adaptive Calibration Technique for High Speed Memory Devices
Method and Apparatus for Scheduling and Using Memory Calibrations to Reduce Memory Errors in High Speed Memory Devices
Method and Apparatus for Restoring Computer Resources
Patent:
6,633,978 →
Application:
09/540,386 →
Embedded Input Logic in a High Input Impedance Strobed Cmos Differential Sense Amplifier
Patent:
6,195,377 →
Application:
09/241,212 →
Persistent Volatile Memory Fault Tracking
System and Method for Signal Synchronization Based on Plural Clock Signals
Fault Detection System
Method and Apparatus for Providing the Proper Voltage to a Memory
System and Method for Controlling Power to Resources Based on Historical Utilization Data
Wide databus architecture
Patent:
6,366,491 →
Application:
09/761,297 →
Esd Protection Clamp for Mixed Voltage I/O Stages Using Nmos Transistors
Patent:
5,780,897 →
Application:
08/555,463 →
Driver Circuit with Precharge and Active Hold
Patent:
5,856,752 →
Application:
08/710,230 →
System and Method for on-Chip Debug Support and Performance Monitoring in a Microprocessor
Patent:
5,867,644 →
Application:
08/711,491 →
Esd Protection System for an Integrated Circuit with Multiple Power Supply Networks
Patent:
5,740,000 →
Application:
08/724,595 →
Input Comparison Circuitry and Method for a Programmable State Machine
Patent:
5,881,217 →
Application:
08/758,606 →
Load and Store Instructions Which Perform Unpacking and Packing of Data Bits in Separate Vector and Inter Cache Storage
Patent:
6,173,366 →
Application:
08/759,044 →
Method of Forming Lightly Doped Drain Region and Heavily Doping a Gate Using a Single Implant Step
Patent:
5,937,302 →
Application:
08/781,092 →
Processor Performance Counter for Sampling the Execution Frequency of Individual Instructions
Patent:
6,112,317 →
Application:
08/815,982 →
Post-Spacer Ldd Implant for Shallow Ldd Transistor
Patent:
5,989,964 →
Application:
08/818,427 →
Thin Polysilicon Masking Technique for Improved Lithography Control
Patent:
5,885,879 →
Application:
08/822,941 →
Method of Making an Igfet Using Solid Phase Diffusion to Dope the Gate, Source and Drain
A Process of Manufacturing a Semiconductor Device Having a Nitrogen Bearing Isolation Region
Patent:
6,057,209 →
Application:
08/891,278 →
High Performance Mosfet Transistor Fabrication Technique
Patent:
5,970,347 →
Application:
08/896,400 →
Memory Controller Supporting Dram Circuits with Different Operating Speeds
Patent:
6,134,638 →
Application:
08/910,847 →
Method and System for Copper Interconnect Formation
Spacer Formation by Poly Stack Dopant Profile Design
Patent:
6,159,814 →
Application:
08/968,444 →
Transistor Fabrication Employing Implantation of Dopant into Junctions Without Subjecting Sidewall Surfaces of a Gate Conductor to Ion Bombardment
Patent:
6,069,046 →
Application:
08/979,282 →
Wide Database Architecture
Patent:
6,195,282 →
Application:
08/986,358 →
Shallow Trench Isolation Formation with No Polish Stop
Patent:
6,090,712 →
Application:
08/992,489 →
Cache Memory Exchange Optimized Memeory Organization for a Computer System
Patent:
6,125,429 →
Application:
09/041,513 →
Esd Protection Clamp for Mixed Voltage I/O Stages Using Nmos Transistors
Patent:
5,932,918 →
Application:
09/072,129 →
Esd Protection Clamp for Mixed Voltage I/O Stages Using Nmos Transistors
Patent:
6,097,071 →
Application:
09/072,130 →
Cache memory exchange optimized memory organization for a computer system
Patent:
6,353,876 →
Application:
09/643,431 →
Related Assignments
(12)
Other recorded transfers of the patents in this record — the chain of ownership.
Change of Address of Assignee
Apr 15, 2009
From: MOSAID TECHNOLOGIES INCORPORATED
To: MOSAID TECHNOLOGIES INCORPORATED
Reel/Frame 022542/0876 →
Assignment of Assignor's Interest
Mar 16, 2011
From: MES, IAN
To: MOSAID TECHNOLOGIES, INCORPORATED
Reel/Frame 025969/0497 →
Assignment of Assignor's Interest
Mar 16, 2011
From: MOSAID TECHNOLOGIES, INCORPORATED
To: MOSAID TECHNOLOGIES INCORPORATED
Reel/Frame 025969/0618 →
U.S. Intellectual Property Security Agreement (for Non-U.S. Grantors) - Short Form
Jan 10, 2012
From: 658276 N.B. LTD.; 658868 N.B. INC.; MOSAID TECHNOLOGIES INCORPORATED
To: ROYAL BANK OF CANADA
Reel/Frame 027512/0196 →
Change of Registered Office Address
Jan 17, 2013
From: BHULLAR, GURPREET; ALLAN, GRAHAM
To: MOSAID TECHNOLOGIES INCORPORATED
Reel/Frame 029646/0328 →
Change of Registered Office Address
Jan 17, 2013
From: MOSAID TECHNOLOGIES INCORPORATED
To: MOSAID TECHNOLOGIES INCORPORATED
Reel/Frame 029646/0343 →
Change of Name
Mar 13, 2014
From: MOSAID TECHNOLOGIES INCORPORATED
To: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
Reel/Frame 032439/0638 →
Release of Security Interest
Aug 7, 2014
From: ROYAL BANK OF CANADA
To: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.; CONVERSANT IP N.B. 868 INC.; CONVERSANT IP N.B. 276 INC.
Reel/Frame 033484/0344 →
Change of Address
Sep 3, 2014
From: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
To: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
Reel/Frame 033678/0096 →
U.S. Patent Security Agreement (for Non-U.S. Grantors)
Sep 9, 2014
From: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
To: CPPIB CREDIT INVESTMENTS INC., AS LENDER; ROYAL BANK OF CANADA, AS LENDER
Reel/Frame 033706/0367 →
Release of U.S. Patent Agreement (for Non-U.S. Grantors)
Oct 12, 2018
From: ROYAL BANK OF CANADA, AS LENDER
To: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
Reel/Frame 047645/0424 →
Release of Security Interest
Oct 30, 2020
From: CPPIB CREDIT INVESTMENTS INC.
To: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
Reel/Frame 054263/0253 →