Multipage program scheme for flash memory
View Patent ↗A circuit and method for programming multiple bits of data to flash memory cells in a single program operation cycle. Multiple pages of data to be programmed into one physical page of a flash memory array are stored in page buffers or other storage means on the memory device. The selected wordline connected to the cells to be programmed is driven with predetermined program profiles at different time intervals, where each predetermined program profile is configured for shifting an erase threshold voltage to a specific threshold voltage corresponding to a specific logic state. A multi-page bitline controller biases each bitline to enable or inhibit programming during each of the time intervals, in response to the combination of specific logic states of the bits belonging to each page of data that are associated with that respective bitline.
1. A multi-page programming method for a NAND flash memory device comprising:
sequentially storing M pages of data in the NAND flash memory device before execution of a single multi-page programming cycle, where M is an integer value greater than 1;
loading bitline access circuitry with the M pages of data; and
initiating, with respect to the M pages of data, the single multi-page programming cycle in the NAND flash memory device for programming the M pages of data to a single physical page of memory cells by storing up to 2 M threshold voltages in memory cells of the NAND flash memory device, wherein the single multi-page programming cycle includes
driving a selected wordline with different time periods for each of 2 M −1 threshold voltages while bitlines are biased to enable or inhibit programming based on a combination of logic states of the M pages of data.
2. The method of claim 1 , further including checking a completion status of the multi-page programming cycle.
3. The method of claim 2 , further including determining if the single multi-page programming cycle was successful when the completion status corresponds to a completed single multipage programming cycle.
4. The method of claim 1 , wherein sequentially storing includes iteratively loading each of the M pages of data into respective M page buffers of the NAND flash memory device.
5. The method of claim 4 , wherein loading each of the M pages of data includes receiving, at the NAND flash memory device, a data load command followed by input data.
6. The method of claim 5 , wherein the input data includes the data and address information.
7. The method of claim 5 , wherein the data load command is a first data load command, and a second data load command is received after the input data corresponding to the first data load command is received.
8. The method of claim 7 , wherein a data end command is received after the input data corresponding to the first data load command is received and before the second data load command is received.
9. The method of claim 7 , wherein a data end command for a last page of the M pages of data is received after input data corresponding to the last page of the M pages of data is received.
10. The method of claim 9 , wherein the data end command includes a multi-page program command.
11. The method of claim 1 , wherein the selected wordline is driven with a programming profile specific to each of 2 M −1 programming iterations while the bit lines are biased to enable or inhibit programming.
12. The method of claim 1 , wherein the single multi-page programming cycle includes 2 M −1 programming iterations, and cells to be programmed with an Nth threshold voltage, where N is an integer value greater than 1 and less than or equal to 2 M −1, are first programmed to the (N−1)th threshold value state in a preceding sequential programming iteration.
13. The method of claim 1 , wherein the single multi-page programming cycle includes 2 M −1 programming iterations, and cells to be programmed with an Nth threshold voltage, where N is an integer value greater than 1 and less than or equal to 2 M −1, are programmed from the erase state to the Nth threshold voltage in a single one of the sequential programming iterations.
14. The method of claim 1 , wherein driving includes driving the selected wordline with increasing time periods for each successive 2 M −1 threshold voltages.
15. A flash memory device comprising:
a memory array having flash memory cells connected to wordlines and coupled to bitlines;
bitline access circuitry for sequentially loading M pages of data before execution of a single multi-page programming cycle and for biasing the bitlines to enable or inhibit programming for each of 2 M −1 programming iterations in response to a combination of bits corresponding to each bitline from the M pages of data during execution of the single multi-page programming cycle, where M is an integer number of at least 2; and
row circuits for driving a selected wordline with different time periods for each of the 2 M −1 programming iterations while the bitlines are biased to enable or inhibit programming based on a combination of logic states of the M pages of data, for programming the M pages of data to a single physical page of memory cells in the single multi-page programming cycle.
16. The flash memory device of claim 15 , wherein the bitline access circuitry includes M data buffers each for storing one of the M pages of data.
17. The flash memory device of claim 16 , wherein the bitline access circuitry includes bitline biasing circuitry for biasing each of the bitlines to enable or inhibit programming in response to the combination of bits of the M pages of data stored in the M data buffers that correspond to each bitline.
18. The flash memory device of claim 17 , wherein each of the M data buffers includes data storage circuits for storing one bit of a page of data.
19. The flash memory device of claim 18 , wherein each bit position of the M data buffers includes
a data verify decoder for receiving the bits of the M pages of data stored in the M data
buffers that correspond to each bitline, and
inversion circuitry for inverting the bits in response to selected outputs of the data decoder.
20. The flash memory device of claim 15 , wherein each of the different time periods increases in time for each successive programming iteration.
21. A flash memory device comprising:
a memory array having flash memory cells connected to wordlines and coupled to bitlines, each flash memory cell being programmable to have a threshold voltage corresponding to one of an erase state, a first state, a second state and a third state;
a bitline access circuit for sequentially loading two pages of data before execution of a single multi-page programming cycle and for biasing the bitlines to program the first state, the second state and the third state in a predetermined order during execution of the single multi-page programming cycle, the bitline access circuit biasing the bitlines to enable or inhibit programming for each of the first state, the second state and the third state in response to specific combinations of bits from the two pages of data; and,
row circuits for driving a selected wordline with different time periods for each of the first state, the second state and the third state to program the two pages of data to a single physical page of flash memory cells in the single multi-page programming cycle while the bitlines are biased for programming the first state, the second state and the third state respectively.
22. A flash memory device comprising:
a memory array having flash memory cells connected to wordlines and coupled to bitlines;
M page buffers for receiving and sequentially storing M pages of data to a single physical row of flash memory cells before execution of a single multi-page programming cycle, where M is an integer number of at least 2;
bitline modulators coupled to each of the bitlines and to the M page buffers, each of the bitline modulators sequentially applying one of 2 M voltage levels to a corresponding bitline in response to a combination of data bits from each of the M pages of data during execution of the single multi-page programming cycle; and
row circuits for driving a selected wordline with at least two different time periods to program the M pages of data to the single physical row of flash memory cells in the single multi-page programming cycle.
23. The flash memory device of claim 22 , wherein a bitline modulator circuit, of the bitline modulators, comprises:
a program data decoder for receiving M bits of data and providing decoded selection signals in response to a logic combination of the M bits of data, wherein each of the M bits of data is associated with one of the M pages of data; and,
a bitline biasing circuit for biasing a bitline to one of the 2 M voltage levels in response to the decoded selection signals.
24. The flash memory device of claim 23 , wherein the bitline biasing circuit biases the corresponding bitlines of the flash memory device to voltage levels effective for one of inhibiting programming and enabling programming of different threshold voltages to flash memory cells coupled to the bitlines in response to logic states of the data bits of the M pages of data.