Patent Assignment
Reel/Frame 033484/0344
Release of Security Interest
Recorded: 2014-08-07
Pages: 110
Assignor
ROYAL BANK OF CANADA
Executed: 2014-06-11
Assignees
CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
11 HINES ROAD, SUITE 203, OTTAWA, ONTARIO, K2K2X1, CANADA
CONVERSANT IP N.B. 868 INC.
44 CHIPMAN HILL, SUITE 1000, SAINT JOHN, NB, E2L 2A9, CANADA
CONVERSANT IP N.B. 276 INC.
570 QUEEN STREET, SUITE 600, FREDERICTON, NB, E3B 6Z6, CANADA
Covered Properties
(1361)
Single Chip Frame Buffer and Graphics Accelerator
Patent:
44,589 →
Application:
12/819,467 →
Delay Locked Loop Implementation in a Synchronous Dynamic Random Access Memory
Semiconductor Memory Asynchronous Pipeline
Semiconductor Memory Asynchronous Pipeline
Process, Voltage, Temperature Independent Switched Delay Compensation Scheme
High Bandwidth Memory Interface
High Bandwidth Memory Interface
Method and Apparatus for Providing a Packet Buffer Random Access Memory
Frequency-Doubling Delay Locked Loop
Port Packet Queuing
High Speed Dram Architecture with Uniform Access Latency
Method and Apparatus for Reducing Pool Starvation in a Shared Memory Switch
Trunking in a Matrix
Method and System for Packet Processing
Congestion Management in a Network
Block Programmable Priority Encoder in a Cam
Patent:
43,552 →
Application:
12/709,198 →
Wide Frequency Range Delay Locked Loop
Double Data Rate Output Circuit and Method
Initialization Circuit for Delay Locked Loop
Charge Pump for Pll/Dll
Delay Locked Loop Circuit and Method
Patent:
43,947 →
Application:
13/105,749 →
Voltage Down Converter for High Speed Memory
Power Up Circuit with Low Power Sleep Mode Operation
Method and System for Accessing a Flash Memory Device
Dynamic Random Access Memory Device and Method for Self-Refreshing Memory Cells
Power Managers for an Integrated Circuit
Low Leakage and Data Retention Circuitry
Systems and Methods for Minimizing Static Leakage of an Integrated Circuit
Sram Leakage Reduction Circuit
Non-Volatile Memory Bank and Page Buffer Therefor
Flash Memory System Control Scheme
Application:
12/855,171 →
Publication:
US US20100325353A1
Non-Volatile Semiconductor Memory with Page Erase
Flash Multi-Level Threshold Distribution Scheme
Low Power Memory Architecture
Dynamic Random Access Memory Device and Method for Self-Refreshing Memory Cells with Temperature Compensated Self-Refresh
Dynamic Random Access Memory with Fully Independent Partial Array Refresh Function
Flash Memory Program Inhibit Scheme
A Double Data Rate Converter Circuit Includes a Delay Locked Loop for Providing the Plurality of Clock Phase Signals
Synchronous Memory Read Data Capture
Apparatus and Method for Establishing Device Identifiers for Serially Interconnected Devices
Data Flow Control in Multiple Independent Port
Apparatus and Method for Producing Ids for Interconnected Devices of Mixed Type
Daisy Chain Cascading Devices with Input/Output Control
Application:
11/496,278 →
Publication:
US US20070076502A1
Daisy Chain Cascading Devices
Asynchronous Id Generation
Daisy Chain Cascade Configuration Recognition Technique
Hybrid Solid-State Memory System Having Volatile and Non-Volatile Memory
Independent Link and Bank Selection
Memory with Output Control
Nonvolatile memory system
Application:
11/639,375 →
Publication:
US US20070165457A1
Nonvolatile Memory System
Application:
12/578,115 →
Publication:
US US20100030951A1
Packet Based Id Generation for Serially Interconnected Devices
Circuit and Method for Testing Multi-Device Systems
Memory System and Method with Serial and Parallel Modes
Address Assignment and Type Recognition of Serially Interconnected Memory Devices of Mixed Type
Circuit for Clamping Current in a Charge Pump
Apparatus and Method for Capturing Serial Input Data
Id Generation Apparatus and Method for Serially Interconnected Devices
Delay Locked Loop Circuit
System and Method of Page Buffer Operation for Memory Devices
Apparatus and Method for Producing Device Identifiers for Serially Interconnected Devices of Mixed Type
Apparatus and Method for Producing Device Identifiers for Serially Interconnected Devices of Mixed Type
Semiconductor Device and Method for Reducing Power Consumption in a System Having Interconnected Devices
Application:
12/018,272 →
Publication:
US US20080201588A1
Non-Volatile Memory with Dynamic Multi-Mode Operation
Bias Generator Providing for Low Power, Self-Biased Delay Element and Delay Line
Voltage Level Shifter and Buffer Using Same
Source Side Asymmetrical Precharge Programming Scheme
Apparatus and Method for Producing Identifiers Regardless of Mixed Device Type in a Serial Interconnection
Apparatus and Method for Communicating with Semiconductor Devices of a Serial Interconnection
Modular Command Structure for Memory and Memory System
Application:
13/016,396 →
Publication:
US US20110131383A1
Methods and Apparatus for Clock Signal Synchronization in a Configuration of Series-Connected Semiconductor Devices
Balanced Pseudo-Random Binary Sequence Generator
Dynamic Impedance Control for Input/Output Buffers
Memory with Data Control
Apparatus and Method of Page Program Operation for Memory Devices with Mirror Back-Up of Data
Dynamic Random Access Memory and Boosted Voltage Producer Therefor
Multi-Level Cell Access Buffer with Dual Function
Daisy-chain memory configuration and usage
Application:
11/897,105 →
Publication:
US US20090063786A1
Pre-Charge Voltage Generation and Power Saving Modes
Reduced Pin Count Interface
Partial Block Erase Architecture for Flash Memory
Non-Volatile Semiconductor Memory Having Multiple External Power Supplies
Non-Volatile Semiconductor Memory Having Multiple External Power Supplies
Patent:
8,300,471 →
Application:
13/096,874 →
Single-Strobe Operation of Memory Devices
Data processing with time-based memory access
Ring-Of-Clusters Network Topologies
Methods and Systems for Failure Isolation and Data Recovery in a Configuration of Series-Connected Semiconductor Devices
Scalable Memory System
Clock Mode Determination in a Memory System
Apparatus and Method for Modeling Coarse Stepsize Delay Element and Delay Locked Loop Using Same
System and Method of Operating Memory Devices of Mixed Type
Data Channel Test Apparatus and Method Thereof
Nonvolatile Semiconductor Memory Device
Semiconductor Memory Device Suitable for Interconnection in a Ring Topology
Memory Controller with Flexible Data Alignment to Clock
Apparatus and Method for Using a Page Buffer of a Memory Device as a Temporary Cache
Method for Stacking Serially-Connected Integrated Circuits and Multi-Chip Device Made from Same
Hierarchical Common Source Line Structure in Nand Flash Memory
Multiple-Bit Per Cell (Mbc) Non-Volatile Memory Apparatus and System Having Polarity Control and Method of Programming Same
Dual Function Compatible Non-Volatile Memory Device
Non-Volatile Semiconductor Memory Device with Power Saving Feature
Non-Volatile Semiconductor Memory Device with Power Saving Feature
Nand Flash Memory Having Multiple Cell Substrates
Clock Reproducing and Timing Method in a System Having a Plurality of Devices
Power Supplies in Flash Memory Devices and Systems
Nand flash memory access with relaxed timing constraints
Application:
12/286,959 →
Publication:
US US20090187701A1
Selective Broadcasting of Data in Series Connected Devices
Apparatus and Method for Identifying Device Types of Series-Connected Devices of Mixed Type
Non-Volatile Memory Device Having Configurable Page Size
Non-Volatile Memory Device Having Configurable Page Size
System Having One or More Memory Devices
Data Storage and Stackable Configurations
Flexible Memory Operations in Nand Flash Devices
Mass Data Storage System with Non-Volatile Memory Modules
Cache Filtering Method and Apparatus
Mixed Data Rates in Memory Devices and Systems
Serial-Connected Memory System with Duty Cycle Correction
Serial-Connected Memory System with Output Delay Adjustment
Data Mirroring in Serial-Connected Memory System
Bridge Device Architecture for Connecting Discrete Memory Devices to a System
Semiconductor Device with Main Memory Unit and Auxiliary Memory Unit Requiring Preset Operation
System Including a Plurality of Encapsulated Semiconductor Chips
Error Detection Method and a System Including One or More Memory Devices
Stacked Semiconductor Devices Including a Master Device
Nand Flash Architecture with Multi-Level Row Decoding
Configurable Module and Memory Subsystem
Bridge Device Architecture for Connecting Discrete Memory Devices to a System
Bridging Device Having a Configurable Virtual Page Size
Bridge Device Having a Virtual Page Buffer
Application:
12/607,680 →
Publication:
US US20100115172A1
Simultaneous Read and Write Data Transfer
Bridging Device Having a Frequency Configurable Clock Domain
Using Interrupted Through-Silicon-Vias in Integrated Circuits Adapted for Stacking
Semiconductor Memory with Multiple Wordline Selection
Package-Level Integrated Circuit Connection Without Top Metal Pads or Bonding Wire
System and Method Providing Interoperability Between Cellular and Other Wireless Systems
Reconfiguring Through Silicon Vias in Stacked Multi-Die Packages
Phase Change Memory Word Line Driver
Semiconductor Memory Device with Plural Memory Die and Controller Die
Multi-Chip Package with Offset Die Stacking
Composite Semiconductor Memory Device with Error Correction
Memory System Having a Plurality of Serially Connected Devices
Method of Configuring Non-Volatile Memory for a Hybrid Disk Drive
Phase Change Memory Array Blocks with Alternate Selection
Application:
13/044,701 →
Publication:
US US20110261613A1
Memory Programming Using Variable Data Width
Phase-Change Memory with Multiple Polarity Bits Having Enhanced Endurance and Error Tolerance
System of Interconnected Nonvolatile Memories Having Automatic Status Packet
Status Indication in a System Having a Plurality of Memory Devices
Application:
13/023,838 →
Publication:
US US20110258366A1
High-Speed Interface for Daisy-Chained Devices
Semiconductor Memory Device with Sense Amplifier and Bitline Isolation
Method and Apparatus for Concurrently Reading a Plurality of Memory Devices Using a Single Buffer
Application:
13/102,310 →
Publication:
US US20110276775A1
Multi-Chip Package with Pillar Connection
Semiconductor Device with Through-Silicon Vias
Multi-Chip Package with Thermal Frame and Method of Assembling
Semiconductor Device with Configurable Through-Silicon Vias
Multipage Program Scheme for Flash Memory
Method, System and Apparatus for Multi-Level Processing
Application:
13/239,977 →
Publication:
US US20120096292A1
Error Detection and Correction Codes for Channels and Memories with Incomplete Error Characteristics
Method and Apparatus for Sharing Internal Power Supplies in Integrated Circuit Devices
Voltage Regulation for 3D Packages and Method of Manufacturing Same
Frequency Division Multiplexing System with Selectable Rate
Local Area Network for Distributing Data Communication, Sensing and Control Signals
Network for Telephony and Data Communication
Network for Telephony and Data Communication
Telephone Outlet for Implementing a Local Area Network Over Telephone Lines and a Local Area Network Using Such Outlets
Network Combining Wired and Non-Wired Segments
Network Combining Wired and Non-Wired Segments
Network Combining Wired and Non-Wired Segments
Network Combining Wired and Non-Wired Segments
Network Combining Wired and Non-Wired Segments
Network Combining Wired and Non-Wired Segments
Telephone Communication System Over a Single Telephone Line
Communication System and Method Over Local Area Network Wiring
Telephone Outlet with Packet Telephony Adapter, and a Network Using Same
Telephone Outlet with Packet Telephony Adaptor, and a Network Using Same
Outlet with Analog Signal Adapter, a Method for Use Thereof and a Network Using Said Outlet
Application:
12/986,539 →
Publication:
US US20110096778A1
Local Area Network of Serial Intelligent Cells
Local Area Network of Serial Intelligent Cells
Local Area Network of Serial Intelligent Cells
Local Area Network of Serial Intelligent Cells
Method and System for Providing Dc Power on Local Telephone Lines
Method and system for providing DC power on local telephone lines
Telephone System Having Multiple Distinct Sources and Accessories Therefor
Telephone system having multiple distinct sources and accessories therefor
Application:
11/712,508 →
Publication:
US US20070153836A1
Modular Outlet
Modular Outlet
Modular Outlet
An Addressable Outlet for Use in Wired Local Area Network
Addressable Outlet, and a Network Using the Same
Application:
12/016,324 →
Publication:
US US20080175256A1
Outlet Add-on Module
Outlet Add-on Module
Outlet Add-on Module
Outlet Add-on Module
Device, method and system for estimating the termination to a wired transmission-line based on determination of characteristic impedance
Word Line Driver in a Hierarchical nor Flash Memory
Temperature Detector in an Integrated Circuit
Position Determination of Mobile Stations in a Wireless Network
Intelligent Video, Data Streaming and Access to Distributed Resources in a Wireless Network
Distributed Network Management Hierarchy in a Multi-Station Communication Network
Adaptive Antenna System for Diversity and Interference Avoidance in a Multi-Station Network
Semiconductor Device Having Metal Lines with Slits
Dynamic Traffic Rearrangement and Restoration for Mpls Networks with Differentiated Services Capabilities
Multi-Hazard Alarm System Using Selectable Power-Level Transmission and Localization
Method and Apparatus for Traversing a Multiplexed Data Packet Stream
Non-Volatile Memory Devices and Control and Operation Thereof
Circuit, System and Method for Selectively Turning Off Internal Clock Drivers
Memory Device and Method for Repairing a Semiconductor Memory
Sequential Pulse Deposition
Application:
13/037,113 →
Publication:
US US20110212628A1
Barrier-Metal-Free Copper Camascence Technology Using Atomic Hydrogen Enhanced Reflow
Integrated Circuitry
Application:
12/612,032 →
Flow-Fill Spacer Structures for Flat Panel Display Device
Mixed Composition Interface Layer and Method of Forming
Patent:
43,025 →
Application:
12/566,533 →
Network Architecture for Data Communication
Charge Pump for Pll/Dll
Termination Circuit for on-Die Termination
Sram Leakage Reduction Circuit
Mixed Composition Interface Layer and Method of Forming
Application:
13/293,778 →
Publication:
US US20120120549A1
System for Transmission Line Termination by Signal Cancellation
Dispersion Tolerant Optical System and Method
Dynamic Random Access Memory and Boosted Voltage Producer Therefor
Semiconductor Device with Recess and Fin Structure
Memory Chip Architecture Having Non-Rectangular Memory Banks and Method for Arranging Memory Banks
Method for Forming a Two-Layered Polysilicon Gater Electrode in a Semiconductor Device Using Grain Boundaries
Patent:
5,441,904 →
Application:
08/341,892 →
Multi-Hazard Alarm System Using Selectable Power-Level Transmission and Localization
Patent:
5,461,365 →
Application:
08/330,901 →
Method of Making Cup-Shaped Dram Capacitor Having an Inwardly Overhang Ing Lip
Patent:
5,518,948 →
Application:
08/534,572 →
Pre-Sense Amplifier for Monolithic Memories
Patent:
5,525,918 →
Application:
08/364,130 →
Method of Multilevel Dram Sense and Restore
Patent:
5,532,955 →
Application:
08/366,921 →
Method for Forming an Oxynitride Film in a Semiconductor Device
Patent:
5,541,141 →
Application:
08/394,607 →
Memory Device with Distributed Voltage Regulation System
Patent:
5,574,697 →
Application:
08/515,485 →
Hierarchical Memory Array Structure Having Electrically Isolated Bit Lines for Temporary Data Storage
Patent:
5,600,602 →
Application:
08/417,213 →
Method of Multilevel Dram Sense and Restore
Patent:
5,612,912 →
Application:
08/584,887 →
Edge Triggered Set-Reset Flip-Flop (Srff)
Patent:
5,633,607 →
Application:
08/430,228 →
Information Transmission System
Patent:
5,636,247 →
Application:
08/407,829 →
Method of Making a Field Effect Transistor Having an Elevated Source and an Elevated Drain
Patent:
5,637,518 →
Application:
08/543,705 →
Self-Locating Remote Monitoring Systems
Patent:
5,650,770 →
Application:
08/547,026 →
Command Encoded Delayed Clock Generator
Patent:
5,652,733 →
Application:
08/638,812 →
Method for Fabricating Semiconductor Memory Element
Patent:
5,654,223 →
Application:
08/495,270 →
Method for Fabricating a Non-Volatile Semiconductor Memory Device Having Storage Cell Array and Peripheral Circuit, and a Structure Thereof
Patent:
5,656,527 →
Application:
07/686,392 →
Wiring Structure for Semiconductor Device and Fabrication Method Therefor
Patent:
5,656,860 →
Application:
08/494,645 →
Multiplication of Storage Capacitance in Memory Cells by Using the Miller Effect
Patent:
5,666,306 →
Application:
08/706,662 →
A Field Effect Transistor
Patent:
5,677,573 →
Application:
08/743,502 →
Circuit for Cancelling and Replacing Redundant Elements
Patent:
5,677,884 →
Application:
08/816,203 →
Power-Up/Power-Down Reset Circuit for Low Voltage Interval
Patent:
5,686,848 →
Application:
08/638,810 →
Data Transmission Installation of the Radio Network Type, and Corresponding Method
Patent:
5,689,510 →
Application:
08/307,579 →
Method and Apparatus for Detecting and Correcting Misconvergence of a Blind Equalizer
Patent:
5,694,423 →
Application:
08/692,554 →
Fabrication Method of Semiconductor Memory Device Containing Cmos Transistors
Patent:
5,696,012 →
Application:
08/772,851 →
Method for Fabricating a Capacitor of a Semiconductor Device
Patent:
5,702,970 →
Application:
08/670,592 →
Interconnection Structure for Attaching a Semiconductor Device to a Substrate
Patent:
5,703,406 →
Application:
08/587,744 →
Multirate Wireless Data Communication System
Patent:
5,706,428 →
Application:
08/615,408 →
Data Loading Circuit for Partial Program of Nonvolatile Semiconductor Memory
Patent:
5,712,818 →
Application:
08/537,615 →
Flexible Dram Array
Patent:
5,712,823 →
Application:
08/597,510 →
Method for Fabricating a Capacitor of a Semiconductor Device and the Structure of the Same
Patent:
5,714,402 →
Application:
08/757,246 →
Method of Manufacturing a Semiconductor Device
Patent:
5,723,363 →
Application:
08/537,062 →
Flexible Dram Array
Patent:
5,724,286 →
Application:
08/355,957 →
Hierarchical Memory Array Structure Having Electrically Isolated Bit Lines for Temporary Data Storage
Patent:
5,724,301 →
Application:
08/752,578 →
Self-Timed Circuit Control Device and Method
Patent:
5,729,160 →
Application:
08/277,580 →
Hierarchical Memory Array Structure with Redundant Components Having Electrically Isolated Bit Lines
Patent:
5,734,620 →
Application:
08/661,810 →
Method of Anti-Fuse Repair
Patent:
5,742,555 →
Application:
08/700,234 →
Data Read Circuit for a Nonvolatile Semiconductor Memory
Patent:
5,748,536 →
Application:
08/652,654 →
Semiconductor Memory Device
Patent:
5,757,692 →
Application:
08/727,852 →
Method for Manufacturing Mosfet
Patent:
5,759,900 →
Application:
08/708,742 →
Method for Manufacturing an Integrated Circuit
Patent:
5,761,082 →
Application:
08/799,493 →
Method of Fabricating Microelectronic Capacitors Having Tantalum Pentoxide Dielectrics and Oxygen Barriers
Patent:
5,763,300 →
Application:
08/709,249 →
Circuit Arrangement and Method for Measuring a Difference in Capacitance Between a First Capacitance C1 and a Second Capacitance C2
Patent:
5,777,482 →
Application:
08/675,590 →
Digital Delay Line for a Reduced Jitter Digital Delay Lock Loop
Patent:
5,777,501 →
Application:
08/638,809 →
Sense Amplifier with Low Power in a Semiconductor Device
Patent:
5,781,041 →
Application:
08/669,746 →
Sub Word Line Driving Circuit and a Semiconductor Memory Device Using the Same
Patent:
5,781,498 →
Application:
08/764,083 →
Method and Circuit for Generating Internal Pulse Signals in Synchronous Memory
Patent:
5,781,500 →
Application:
08/850,247 →
Delay Locked Loop Implementation in a Synchronous Dynamic Random Access Memory
Patent:
5,796,673 →
Application:
08/319,042 →
Synchronous Memory Device Having Dual Input Registers of Pipeline Structure in Data Path
Patent:
5,796,675 →
Application:
08/796,219 →
Combined Field/Trench Isolation Region Fabrication Methods
Patent:
5,804,491 →
Application:
08/744,436 →
Thin Film Transistor for Antistatic Circuit and Method for Fabricating the Same
Patent:
5,807,728 →
Application:
08/774,824 →
Integrated Circuits, and Methods of Fabricating Same, Which Take into Account Capacitive Loading by the Integrated Circuit Potting Material
Patent:
5,808,366 →
Application:
08/694,541 →
Staggered Pipeline Access Scheme for Synchronous Random Access Memory
Patent:
5,808,959 →
Application:
08/612,044 →
Memory Device with Distributed Voltage Regulation System
Patent:
5,818,780 →
Application:
08/717,170 →
Circuit and Method for Testing a Memory Device with a Cell Plate Generator Having a Variable Current
Patent:
5,822,258 →
Application:
08/851,416 →
Field Effect Transistor Comprising Electrically Conductive Plugs Having Monocrystalline and Polycrystalline Silicon
Patent:
5,831,334 →
Application:
08/912,899 →
Fabricating Method of a Fin Shaped Capacitor
Patent:
5,834,357 →
Application:
08/550,326 →
Nonvolatile Memory Device Having an Improved Integration and Reduced Contact Failure
Patent:
5,834,807 →
Application:
08/615,064 →
Integrated Circuit Test Head
Patent:
5,834,946 →
Application:
08/961,412 →
Multiplication of Storage Capacitance in Memory Cells by Using the Miller Effect
Patent:
5,835,403 →
Application:
08/879,908 →
Sub Word Line Driving Circuit and a Semiconductor Memory Device Using the Same
Patent:
5,835,439 →
Application:
08/887,280 →
Circuit for Canceling and Replacing Redundant Elements
Patent:
5,838,620 →
Application:
08/796,148 →
Distributed Serial Control System
Patent:
5,841,360 →
Application:
08/734,921 →
Built in Access Time Comparator
Patent:
5,844,916 →
Application:
08/429,544 →
Method for Removing Defects by Ion Implantation Using Medium Temperature Oxide Layer
Patent:
5,846,887 →
Application:
08/757,161 →
Voltage Detection Circuit and Internal Voltage Clamp Circuit
Patent:
5,847,591 →
Application:
08/829,256 →
Closed-Mold for Led Alphanumeric Displays
Patent:
5,855,924 →
Application:
08/579,535 →
Microelectronic Capacitors Having Tantalum Pentoxide Dielectrics and Oxgen Barriers
Patent:
5,859,760 →
Application:
08/843,799 →
Renumbered Array Architecture for Multi-Array Memories
Patent:
5,859,961 →
Application:
08/656,164 →
Single Sideband Double Quadrature Modulator
Patent:
5,861,781 →
Application:
08/931,370 →
Memory Device Having Divided Global Bit Lines
Patent:
5,864,497 →
Application:
08/961,544 →
Method for Forming Contact Hole of Semiconductor Device
Patent:
5,869,404 →
Application:
08/847,811 →
Current Mode Digital to Analogue Converter
Patent:
5,870,049 →
Application:
08/838,168 →
Staggered Pipeline Access Scheme for Synchronous Random Access MEM0RY
Patent:
5,872,742 →
Application:
09/063,529 →
Word Line Driver for Semiconductor Memories
Patent:
5,875,149 →
Application:
08/828,817 →
Data-Bit Redundancy in Semiconductor Memories
Patent:
5,877,992 →
Application:
09/000,954 →
Semiconductor Device Fabrication Method
Patent:
5,882,968 →
Application:
08/576,752 →
Interconnection Structure for Attaching a Semiconductor to Substrate
Patent:
5,883,438 →
Application:
08/854,069 →
Flexible Dram Array
Patent:
5,903,511 →
Application:
08/999,002 →
A Method for Developing Shallow Trench Isolation in a Semiconductor Memory Device
Patent:
5,904,538 →
Application:
08/923,141 →
Method of Forming a Polycide Gate of a Semiconductor Device
Patent:
5,908,791 →
Application:
08/643,885 →
Circuit for Cancelling and Replacing Redundant Elements
Patent:
5,912,579 →
Application:
09/133,586 →
Method for Forming Texturized Polysilicon
Patent:
5,913,128 →
Application:
08/959,648 →
Semiconductor Apparatus Having a Leadframe with Coated Leads
Patent:
5,923,080 →
Application:
08/960,081 →
Method of Fabrication a Source/Drain with Ldd and Halo
Patent:
5,937,293 →
Application:
09/057,537 →
Reticle Cleaning Without Damaging Pellicle
Patent:
5,938,860 →
Application:
08/921,656 →
Circuit and Method for Testing a Memory Device with a Cell Plate Generator Having a Variable Current
Patent:
5,943,276 →
Application:
09/031,973 →
Delay-Locked Loop with Binary-Coupled Capacitor
Patent:
5,946,244 →
Application:
08/811,918 →
Chemical Vapor Deposition of Titanium from Titanium Tetrachloride and Hydrocarbon Reactants
Patent:
5,946,594 →
Application:
08/581,765 →
Microprocessor Power Control System
Patent:
5,951,689 →
Application:
08/775,629 →
Method for Fabricating a Capacitor of a Semiconductor Device
Patent:
5,953,576 →
Application:
08/925,060 →
Column Redundancy in Semiconductor Memories
Patent:
5,959,903 →
Application:
08/904,153 →
Self-Locating Remote Monitoring Systems
Patent:
5,963,130 →
Application:
08/849,998 →
Bipolar Silicon Transistor with Arsenic and Phosphorous Ratio
Patent:
5,965,929 →
Application:
08/623,905 →
Integrated Circuit Memory Devices with High and Low Dopant Concentration Regions of Different Diffusivities
Patent:
5,969,395 →
Application:
08/854,874 →
Power Savings Technique in Solid State Integrated Circuits
Patent:
5,973,552 →
Application:
08/743,348 →
Integrated Circuitry Fuse Forming Methods, Integrated Circuitry Programming Methods, and Related Integrated Circuitry
Patent:
5,976,917 →
Application:
09/015,414 →
Method of Anti-Fuse Repair
Patent:
5,978,248 →
Application:
09/030,130 →
Input/Output Device Having Shared Active Area
Patent:
5,978,287 →
Application:
08/781,490 →
Method and Apparatus for Evaluating Internal Film Stress at High Lateral Resolution
Patent:
5,979,244 →
Application:
09/034,517 →
Bi-Directional Data Bus Scheme with Optimized Read and Write Characters
Patent:
5,982,674 →
Application:
09/163,341 →
A Method for Fabricating a Semiconductor Device
Patent:
5,985,734 →
Application:
08/979,235 →
Dynamic Random Access Memory Device and Method for Fabricating the Same
Patent:
5,990,510 →
Application:
09/212,053 →
Address Counter Cell
Patent:
5,991,226 →
Application:
08/995,991 →
A Trench Isolation Structure of a Semiconductor Device and a Method for Thereof
Patent:
5,994,200 →
Application:
08/898,574 →
Multiplication of Storage Capacitance in Memory Cells by Using the Miller Effect
Patent:
5,995,410 →
Application:
09/123,634 →
Semiconductor Constructuions Comprising Electrically Conductive Plugs Having Monocrystalline and Polycrystalline Silicon
Patent:
5,998,844 →
Application:
09/153,088 →
Method for Reducing Gaseous Species of Contamination in Wet Processes
Patent:
6,001,189 →
Application:
08/724,578 →
Cell Array and Sense Amplifier Structure Exhibiting Improved Noise Characteristic and Reduced Size
Patent:
6,002,625 →
Application:
08/991,618 →
Polishing Systems Methods of Polishing Substrates and Method of Preaparing Liquids for Semiconductor Fabrication Process.
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Memory Device with Distributed Voltage Regulation System
Patent:
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Word Line Driver for Semiconductor Memories
Patent:
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Application:
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Method for Fabricating Field Effect Transistor
Patent:
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Gapped-Plate Capacitor
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Methods of Forming Field Effect Transistors and Related Field Effect Transistor Constructions
Patent:
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Application:
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Shared Length Cell for Improved Capacitance
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Methods of Designing and Fabricating Intergrated Circuits Which Take into Account Capacitive Loading by the Intergrated Circuit Potting Material
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Application:
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Graphical Editor for Defining Memory Test Sequences
Patent:
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Semiconductor Device Having Capacitor
Patent:
6,034,392 →
Application:
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Method of Making a Capacitor
Patent:
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Application:
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Methods of Forming Electrically Interconnected Lines Using Ultraviolet Radiation as an Organic Compound Cleaning Agent
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Method for Designing Cell Array Layout of Non-Volatile Memory Device
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Method of Making a Field Effect Transistor Having an Elevated Source and an Elevated Drain
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Wiring Structure for Semiconductor Device and Fabrication Method Therefor
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Application:
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Regulated Dram Cell Plate and Precharge Voltage Generator
Patent:
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Application:
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Method for Isolating Semiconductor Devices
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Ball Grid Array Package
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Reticle Cleaning Without Damaging Pellicle
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Cell Capacitors, Memory Cells, Memory Arrays, and Method of Fabrication
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Synchronous Dynamic Random Access Memory in a Semiconductor Memory Device
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Method for Manufacturing a Capacitor of a Semiconductor Device
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Methods of Fabricating Conductive Lines in Integrated Circuits Using Insulating Sidewall Spacers and Conductive Lines So Fabricated
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Delayed Locked Loop Implementation in a Synchronous Dynamic Random Access Memory
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Contact Structure of Semiconductor Memory Device for Reducing Contact Related Defect and Contact Resistance and Method for Forming the Same
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Methods for Preparing Ruthenium Metal Films
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Address Counter Cell
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Circuits and Methods for Selectively Coupling Redundant Elements into an Integrated Circuit
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Semiconductor Device for Improving Short Channel Effect
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Fin-Shaped Capacitor
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Method for Fabricating a Capacitor of a Semiconductor Device
Patent:
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Clock Signal Phase Comparator
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Digital Delay Locked Loop
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Low Voltage Transistor Structure Having a Grooved Gate
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Source Regulation Circuit for an Erase Operation of Flash Memory
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Application:
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Alphanumeric Display with 21-Dot Matrix Format
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Method of Fabricating Gate Electrodes of Twin-Well Cmos Device
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Method for Fabricating a Semiconductor Device Having a Tapered Contact Hole
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Boride Electrodes and Barriers for Cell Dielectrics
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Planarization Method for a Semiconductor Device
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Multi-Chip Package
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Method of Preventing Bowing in a via Formation Process
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Methods for Preparing Ruthenium Oxide Films
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Bi-Directional Data Bus Scheme with Optimized Read and Write Characters
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Voltage Generator with First Drive Current in Test Mode and Second Drive Current in Normal Operation
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Dilute Composition Cleaning Method
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Column Redundancy Circuit with Reduced Signal Path Delay
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Semiconductor Chip Package and Method for Fabricating the Same
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Application:
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Column Redundancy in Semiconductor Memories
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Apparatus and Method for Increasing Test Flexibility of a Memory Device
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Application:
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Sense Amplifier Driving Device
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Application:
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Improved Redundancy Selection Circuit for Semiconductor Memories
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Application:
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Solvent Prewet and Method to Dispense the Solvent Prewet
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Adjusable Substrate Voltage Applying Circuit of a Semiconductor Device
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Application:
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Method for Multilevel Dram Sensing
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Cell Capacitors, Memory Cells, Memory Arrays, and Method of Fabrication
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Delay Locked Loop Device of the Semiconductor Circuit
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Method for Fabricating a Surface Mounting Type Semiconductor Chip Package
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Method for Forming Integrated Circuit Memory Devices with High and Low Dopant Concentration Regions of Different Diffusivities
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Reticle Cleaning Without Damaging Pellicle
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Application:
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Method for Detecting or Repairing Intercell Defects in More Than One Array of a Memory Device
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Orthogonal Frequency Division Multiplexing System with Dynamically Scalable Operating Parameters and Method Thereof
Patent:
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Shared Length Cell for Improved Capacitance
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Application:
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Bist Memory Test System
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Application:
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Chemical Vapor Deposition of Titanium from Titanium Tetrachloride and Hydrocarbon Reactants
Patent:
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Application:
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Self-Locating Remote Monitoring Systems
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Application:
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Plural Memory Banks Memory Device That Can Simultaneously Read from or Write to All of the Memory Banks During Testing
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Device and Method for Repairing a Semiconductor Memory
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Polishing Systems, Methods of Polishing Substrates, and Methods of Preparing Liquids for Semiconductor Fabrication Processes
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Application:
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Apparatus and Method for Performing Data Read Operation in Ddr Sdram
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Application:
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Method of Forming High Aspect Ratio Structures for Seminconductor Devices
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Application:
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Delayed Locked Loop Implementation in a Synchronous Dynamic Random Access Memory
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Application:
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Polishing Systems, Methods of Polishing Substrates, and Methods of Preparing Liquids for Semiconductor Fabrication Processes
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Application:
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Method of Forming Capacitor of Semiconductor Device
Patent:
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Application:
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Thin Film Transistor for Antistatic Circuit and Method for Fabricating the Same
Patent:
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Application:
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Circuit for Cancelling and Replacing Redundant Elements
Patent:
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Application:
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A Semiconductor Memeory Device Having Plural Memory Cell Arrays Divided into Plural Bank Sections
Patent:
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Application:
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Semiconductor chip package and method for fabricating the same
Patent:
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Method of Forming a Capacitor and a Capacitor Construction
Patent:
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Application:
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Method of Forming a Capacitor
Patent:
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Application:
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Method for an Erase Operation of Flash Memory Using a Source Regulation Circuit
Patent:
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Application:
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A Semiconductor Circuit Design Method for Employing Spacing Constraints and Circuits Thereof
Patent:
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Application:
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Cell Capacitors, Memory Cells, Memory Arrays, and Method of Fabrication
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Semiconductor Device Having Triple-Well
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Application:
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Method of anti-fuse repair
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Application:
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Integrated Circuitry Fuse Forming Methods, Integrated Circuitry Programming Methods, and Related Integrated Circuitry
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Application:
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Method for Fabricating a Dram Cell Capacitor Including Etching Upper Conductive Layer with Etching Byproduct Forming a Etch Barrier on the Conductive Pattern
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Application:
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Delay Locked Loop Using Bidirectional Delay
Patent:
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Application:
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Semiconductor Device Having Capacitor and Method of Fabricating the Same
Patent:
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Application:
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Integrated Circuitry Fuse Forming Methods, Integrated Circuitry Programming Methods, and Related Integrated Circuitry
Patent:
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Application:
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Method of fabricating self-aligning stacked capacitor using electroplating method
Patent:
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Application:
09/551,524 →
Trench Isolation Method
Patent:
6,255,194 →
Application:
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Delay-locked loop with binary-coupled capacitor
Patent:
6,256,259 →
Application:
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Method for Fabricating a Semiconductor Device
Patent:
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Application:
08/773,174 →
Etch Barrier Structure of a Semiconductor Device and Method for Fabricating the Same
Patent:
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Application:
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Delay-locked loop with binary-coupled capacitor
Patent:
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Application:
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Integrated circuitry fuse forming methods, integrated circuitry programming methods, and related integrated circuitry
Patent:
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Application:
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Organic Field Ionization Source
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Application:
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Methods and Solutions for Cleaning Polished Aluminum-Containing Layers, Methods for Making Metallization Structures, and the Structures Resulting from These Methods
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6,265,781 →
Application:
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Methods of Forming Self-Aligned Contact Pads on Electrically Conductive Lines
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Trench Isolation Method for Semiconductor Integrated Circuit
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Surface cleaning apparatus
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Application:
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Method of Making a Dynamic Random Access Memory Device Utilizing Chemical Mechanical Polishing
Patent:
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Graded Layer for Use in Semiconductor Circuits and Method for Making Same
Patent:
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Application:
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Surface Cleaning Apparatus and Method
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Application:
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Method of Forming a Pair of Capacitors Having a Common Capacitor Electrode, Method of Forming Dram Circuitry, Integrated Circuitry and Dram Circuitry
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Semiconductor Constructions Comprising Aluminum-Containing Layers
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Electrostatic Method and Apparatus for Vaporizing Precursors and System for Using Same
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Methods for preparing ruthenium oxide films
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Double Layer Electrode and Barrier System on Hemispherical Grain Silicon for Use with High Dielectric Constant Materials and Methods for Fabricating the Same
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Reticle cleaning without damaging pellicle
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Solvent prewet and method and apparatus to dispense the solvent prewet
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Circuit for Standby Current Reduction
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Application:
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Stackable Ball Grid Array Semiconductor Package and Fabrication Method Thereof
Patent:
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Application:
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Method of Forming Dram Trench Capacitor with Metal Layer Over Hemispherical Grain Polysilicon
Semiconductor Device Having Improved on-Off Current Characteristics
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6,291,865 →
Application:
09/217,574 →
Phase Splitter
Patent:
6,292,042 →
Application:
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Method for Fabricating Contact Pad for Semiconductor Device
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Application:
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Integrated Circuitry Fuse Forming Methods, Integrated Circuitry Programming Methods, and Related Integrated Circuitry
Patent:
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Application:
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Method of Forming a Capacitor
Method for forming a gate electrode on a semiconductor substrate
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Application:
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Memory Device with Distributed Voltage Regulation System
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Application:
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Method for forming multi-layer interconnection of a semiconductor device
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Dilute Cleaning Composition and Method for Using Same
Patent:
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Application:
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Capacitor and method of forming a capacitor
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Application:
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Semiconductor memory having segmented row repair
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Application:
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Delayed locked loop implementation in a synchronous dynamic random access memory
Gapped-Plate Capacitor
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Application:
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Thermal Processing of Metal Alloys for an Improved Cmp Process in Integrated Circuit Fabrication
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Deadhesion Method and Mechanism for Wafer Processing
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Application:
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Boride Electrodes and Barriers for Cell Dielectrics
Patent:
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Application:
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Method for Improved Processing and Etchback of a Container Capacitor
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Methods of Making Semiconductor Devices
Patent:
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Dynamic content addressable memory cell
Patent:
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Application:
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Diffusion Barrier Layers and Methods of Forming Same
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Application:
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Data input circuit of semiconductor memory device
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Application:
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Circuit and method for testing a memory device
Patent:
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Application:
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Process, Voltage, Temperature Independent Switched Delay Compensation Scheme
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Application:
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Method and Apparatus for Controlling Rate of Pressure Change in a Vacuum Process Chamber
A Semiconductor Memory Array Layout
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Hierarchical Data Storage Management
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Application:
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Trench isolation structure, semiconductor device having the same, and trench isolation method
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Application:
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Semiconductor device and method for fabricating the same
Circuits and methods for selectively coupling redundant elements into an integrated circuit
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Methods of forming field effect transistors and related field effect transistor constructions
Methods of forming field effect transistors and related field effect transistor constructions
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Metallization Process for Manufacturing Semiconductor Devices
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Application:
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Impurity Ion Segregation Precluding Layer, Fabrication Method Thereof, Isolation Structure for Semiconductor Device Using the Impurity Ion Segregation Precluding Layer and Fabricating Method Thereof
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Method for Fabricating a Semiconductor Memory Device and the Structure Thereof
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Digital delay locked loop
Patent:
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Semiconductor Processing Methods of Polishing Aluminum-Comprising Layers
Patent:
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Application:
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Chemical vapor deposition of titanium from titanium tetrachloride and hydrocarbon reactants
Methods of Forming Materials Comprising Tungsten and Nitrogen
Capacitor for Semiconductor Memory Device and Fabrication Method Thereof
Patent:
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Application:
09/417,775 →
Method for Fabricating Semiconductor Device
Method of fabricating an SrRuO3 Film
Patent:
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Application:
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Method of fabricating floating gates in semiconductor device
Patent:
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Application:
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Methods of forming field effect transistors and related field effect transistor constructions
Patent:
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Method for fabricating a semiconductor memory device
Patent:
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Application:
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Wiring Structure of Semiconductor Device and Method for Manufacturing the Same
Patent:
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Application:
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Selective Method to Form Roughened Silicon
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Application:
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Method for Forming Gate Oxide Film in Semiconductor Device
Patent:
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Application:
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Semiconductor memory device having operation delay function of column address strobe command, and buffer and signal transmission circuit which are applied to the semiconductor memory device
Polysilicon-Silicon Dioxide Cleaning Process Performed in an Integrated Cleaner with Scrubber
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Circuit and method for testing a memory device
Patent:
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Application:
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Binary-Ternary Content Addressable Memory
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09/684,589 →
Method of Depositing a Nitrogen Enriched Metal Layer, Method of Forming a Silicide Contact to a Silicon Comprising Substrate, Method of Forming a Metal Source Layer in an Integrated Circuit, Method of Analyzing Impact of Operating Parameter Changes for a Plasma Depositio
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6,365,507 →
Application:
09/260,237 →
Method and System for State-Dependent Admission Control and Routing of Multi-Rate Circuit-Switched Traffic
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Enhanced Capacitor Shape
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Application:
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Efficient Digital Itu-Compliant Zero-Buffering Dtmf Detection Using the Non-Uniform Discrete Fourier Transform
Patent:
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Method of Forming a Capacitor Container Electrode and Method of Patterning a Metal Layer by Selectively Silicizing the Electrode or Metal Layer and Removing the Silicized Portion
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Application:
09/586,321 →
Shared Length Cell for Improved Capacitance
Method for Multilevel Dram Sensing
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Multilevel dram sense amplifier
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Application:
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Method of Manufacturing a Capacitor Having Oxide Layers with Different Impurities and Method of Fabricating a Semiconductor Device Comprising the Same
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Method of Forming Memory Circuitry and Method of Forming Memory Circuitry Comprising a Buried Bit Line Array of Memory Cells
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Semiconductor Device and Method of Fabricating the Same
Methods for Forming Contact and Container Structures, and Integrated Circuit Devices Therefrom
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Method of Forming T-Shaped Isolation Layer, Method of Forming Elevated Salicide Source/Drain Region Using the Same, and Semiconductor Device Having T-Shaped Isolation Layer
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Application:
09/573,268 →
Dilute Cleaning Composition
Multi-stage lookup for translating between signals of different bit lengths
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Semiconductor Memory Device Having a Plurality of Banks Sharing a Column Control Unit
Methods of Forming Semiconductor Circuit Constructions and Capacitor Constructions
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Method for Fabricating a Capacitor of a Semiconductor Device and a Capacitor Made Thereby
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Application:
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Analog Mixed Digital Dll
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Application:
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Asynchronous SRAM compatible memory device using DRAM cell and method for driving the same
Sleepmode Activation in a Slave Device
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Reticle Cleaning Without Damaging Pellicle
Method of Forming a Capacitor
Methods of Forming Materials Comprising Tungsten and Nitrogen, and Methods of Forming Capacitors
Chemical Treatment of Semiconductor Substrates
Patent:
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Application:
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Communications and Control Network Having Multiple Power Supplies
Patent:
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Application:
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Double Layer Electrode and Barrier System on Hemispherical Grain Silicon for Use with High Dielectric Constant Materials and Methods for Fabricating the Same
Multilayer Passivation Process for Forming Air Gaps Within a Dielectric Between Interconnections
Methods of Forming Field Effect Transistors and Related Field Effect Transistor Constructions
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Application:
09/490,257 →
Synchronous Feedback Digital Circuit Having a Minimzed Switching Power Loss
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Application:
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Delay-Locked Loop with Binary-Coupled Capacitor
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Methods of Forming Capacitors and Resultant Capacitor Structures
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09/389,533 →
Tungsten layer formation method for semiconductor device and semiconductor device using the same
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Application:
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Methods of Forming Field Effect Transistors and Related Field Effect Transistor Constructions
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Application:
09/494,973 →
Stackable Ball Grid Array Semiconductor Package and Fabrication Method Thereof
Composition and Method of Formation and Use Therefor in Chemical-Mechanical Polishing
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Application:
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Memory Cell Arrays Comprising Intersecting Slanted Portions
Patent:
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Application:
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Methods of Forming Field Effect Transistors
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Method of Producing an Etch Pattern
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Application:
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Multi-Stage Lookup for Translating Between Signals of Different Bit Lengths
Planarization Method of Insulating Layer for Semiconductor Device
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Sense Amplifier Circuit for Use in a Semiconductor Memory Device
Method and Apparatus for Inspecting Wafers
Reduction of Surface Roughness During Chemical Mechanical Planarization(Cmp)
Patent:
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Application:
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Dram Cell Constructions, and Methods of Forming Dram Cells
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Application:
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Methods of Forming Capacitors
Organic Field Ionization Source
Cell Capacitors, Memory Cells, Memory Arrays, and Method of Fabrication
Patent:
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Non-Volatile Semiconductor Memory Device Capable of Reducing Read Time
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Application:
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Nonvolatile Memory Devices Having Alternative Programming
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Method and Apparatus for Selectively Disabling Logic in a Semiconductor Device
Patent:
6,434,077 →
Application:
09/804,988 →
Adaptive Layered Coding for Voice Over Wireless Ip Applications
Patent:
6,434,191 →
Application:
09/653,913 →
Encryption Processor with Shared Memory Interconnect
Patent:
6,434,699 →
Application:
09/584,930 →
Semiconductor Circuit Design Methods, Semiconductor Processing Methods and Integrated Circuitry
Collimated Sputter Deposition Monitor Using Sheet Resistance
Patent:
6,436,246 →
Application:
08/788,980 →
Collimated Sputter Deposition Monitor Using Sheet Resistance
Trench Isolation Method for Semiconductor Integrated Circuit
Patent:
6,436,611 →
Application:
09/611,799 →
Mosfet Device Fabrication Method Capable of Allowing Application of Self-Aligned Contact Process While Maintaining Metal Gate to Have Uniform Thickness
Delay Locked Loop Incorporating a Ring Type Delay and Counting Elements
Method for Producing Water for Use in Manufacturing Semiconductors
Patent:
6,440,382 →
Application:
09/387,119 →
Frequency-Doubling Delay Locked Loop
Patent:
6,441,659 →
Application:
09/562,024 →
Semiconductor Memory Having Segmented Row Repair
Method and Apparatus for Traversing a Multiplexed Data Packet Stream
Patent:
6,442,329 →
Application:
09/259,398 →
Devices for Controlling Temperature Indications in Integrated Circuits Using Adjustable Threshold Temperatures
Patent:
6,442,500 →
Application:
09/359,438 →
Semiconductor Memory Device Having a Plurality of Laser Fuses
Patent:
6,448,626 →
Application:
09/672,924 →
Method for Fabricating Semiconductor Device Having a Capacitor
Graded Layer for Use in Semiconductor Circuits and Method for Making Same
System and Method for Selectively Increasing Surface Temperature of an Object
Method and Apparatus for the Fabrication of Ferroelectric Films
Reticle Cleaning Without Damaging Pellicle
Patent:
6,458,216 →
Application:
09/543,036 →
Isolation and/or Removal of Ionic Contaminants from Planarization Fluid Compositions Using Macrocyclic Polyethers
Patent:
6,458,290 →
Application:
09/642,682 →
Semiconductor Chip Package and Method of Fabricating Same
Patent:
6,458,627 →
Application:
09/415,267 →
Method of Selective Oxidation in Semiconductor Manufacture
Patent:
6,458,714 →
Application:
09/721,839 →
Capacitor Structure
Patent:
6,459,116 →
Application:
09/283,606 →
Integrated Circuit Capacitor Structures
Apparatus and Method for Increasing Test Flexibility of a Memory Device
Patent:
6,459,635 →
Application:
09/703,360 →
Process for Fabricating Rusixoy-Containing Adhesion Layers
Patent:
6,461,909 →
Application:
09/651,859 →
Rusixoy-Containing Adhesion Layers
Semiconductor Memory Device with Redundancy Logic Cell and Repair Method
Direct Memory Access Execution Engine with Indirect Addressing of Circular Queues in Addition to Direct Memory Addressing
Patent:
6,463,059 →
Application:
09/205,480 →
Methods of Forming Self-Aligned Contact Pads on Electrically Conductive Lines
Trench Isolatoin Regions Having Trench Liners with Recessed Ends
Method and Apparatus for Switchably Selecting an Integrated Circuit Operating Mode
Patent:
6,466,048 →
Application:
09/862,339 →
Non-Volatile Semiconductor Memory Device
Patent:
6,466,478 →
Application:
09/847,115 →
Isolation and/or Removal of Ionic Contaminants from Planarization Fluid Compositions Using Macrocyclic Polyethers and Methods of Using Such Compositions
Patent:
6,468,909 →
Application:
09/146,299 →
Methods of Forming Field Effect Transistors and Related Field Effect Transistor Constructions
Method of Forming a Contact Plug for a Semiconductor Device
Patent:
6,472,303 →
Application:
10/034,242 →
Bit Line Sensing Control Circuit for a Semiconductor Memory Device and Layout of the Same
Methods of Forming Field Effect Transistors and Related Field Effect Transistor Constructions
Sensor Devices, Methods and Systems for Detecting Gas Phase Materials
Patent:
6,479,297 →
Application:
09/652,634 →
Method of Forming Interlevel Dielectric Layer of Semiconductor Device
Reduced Area Sense Amplifier Isolation Layout in a Dynamic Ram Architecture
Patent:
6,480,407 →
Application:
08/519,504 →
Local Area Network of Serial Intelligent Cells
Patent:
6,480,510 →
Application:
09/123,486 →
Methods of Forming Field Effect Transistors and Related Field Effect Transistor Constructions
Nonvolatile Semiconductor Memory Device and Manufacturing Method Thereof
Dynamic Content Addressable Memory Cell
Multi-State Non-Volatile Semiconductor Memory Device
Delay-Locked Loop with Binary-Coupled Capacitor
Interface Circuit for Using in High-Speed Semiconductor Device and Interfacing Method
Sdram Having Posted Cas Function
Method and Apparatus for Connecting Network Segments
Patent:
6,483,852 →
Application:
09/210,456 →
Reducing Asymmetrically Deposited Film Induced Registration Error
Delay Locked Loop with Delay Control Unit for Noise Elimination
Level-Shifting Reference Voltage Source Circuits and Methods
Delay-Locked Loop with Binary-Coupled Capacitor
Delay-Locked Loop with Binary-Coupled Capacitor
Methods of Forming Capacitors and Resultant Capacitor Structures
Solutions of Metal-Comprising Materials, Methods of Forming Metal-Comprising Layers, Methods of Storing Metal-Comprising Materials, and Methods of Forming Capacitors
Sysrem for Testing Integrated Circuit Devices
Patent:
6,496,027 →
Application:
08/916,994 →
Gapped-Plate Capacitor
Patent:
6,498,363 →
Application:
09/652,837 →
Semiconductor Memory Device Having a Memory Block with a Decreased Capacitance
Reticle Cleaning Without Damaging Pellicle
Semiconductor Device Having Trench Isolation Structure and Method of Forming Same
Bitline Precharge
Method of Fabricating an SRRUO3 Film
Method of Manufacturing Semiconductor Devices with Titanium Aluminum Nitride Work Function
Deadhesion Method and Mechanism for Wafer Processing
Capacitor for Semiconductor Memory Device
Patent:
6,507,062 →
Application:
10/013,402 →
Aluminum-Beryllium Alloys for Air Bridges
Patent:
6,509,590 →
Application:
09/119,355 →
High Bandwidth Memory Interface
Method for Detecting or Repairing Intercell Defects in More Than One Array of a Memory Device
Patent:
6,510,533 →
Application:
09/749,854 →
Method for Making High K Dielectric Gate for Semiconductor Device
Method of Forming a Gate Electrode in a Semiconductor Device
Patent:
6,514,826 →
Application:
09/721,636 →
Wafer Polishing Slurry and Chemical Mechanical Polishing (Cmp) Method Using the Same
Nanotube Semiconductor Devices and Methods for Making the Same
Patent:
6,515,325 →
Application:
10/092,829 →
Method of Anti-Fuse Repair
Solvated Ruthenium Precursors for Direct Liquid Injection Ofruthenium and Ruthenium Oxide
Methods of Forming Nitrogen-Containing Masses, Silicon Nitride Layers, and Capacitor Constructions
Boride Electrodes and Barriers for Cell Dielectrics
Rhodium-Rich Oxygen Barriers
Method of Forming Low Dielectric Silicon Oxynitride Spacer Films Highly Selective to Etchants
Patent:
6,518,626 →
Application:
09/507,463 →
Voice-Activated Personal Alarm
Circuit and Method for Controlling Buffers in Semiconductor Memory Device
Method for Reducing Gaseous Species of Contamination in Wet Processes
Patent:
6,521,049 →
Application:
09/327,152 →
Column Transistor for Semiconductor Devices
Semiconductor Constructions Compromising Aluminum-Containing Layers
Content Addressable Memory Cell Having Improved Layout
Searchline Control Circuit and Power Reduction Method
Stereolithographic Method for Applying Materials to Electronic Component Substrates and Resulting Structures
Patent:
6,524,346 →
Application:
09/259,143 →
Platinum-Rhodium Stack as an Oxygen Barrier
Duty Correction Circuit and a Method of Correcting a Duty
Patent:
6,525,581 →
Application:
10/033,989 →
Method and Apparatus for Determining Interpolated Intermediate Values of a Sampled Signal
Reference Voltage Generator
Integrated Circuit Configuration for Testing Transistors, and a Semiconductor Wafer Having Such a Circuit Configuration
Source Regulation Circuit for Flash Memory
Method for Depositing a Tungsten Silicide Layer
Semiconductor Memory Device Having Capacitor Structure Formed in Proximity to Corresponding Transistor
Pattern Formation Method Using Two Alternating Phase Shift Masks
Method of Forming Semiconductor Device Having a Gaa Type Transistor
Digitally Controlled Pulse Width Adjusting Circuit
Patent:
6,538,465 →
Application:
10/084,620 →
Semiconductor Memory Asynchronous Pipeline
Solvated Ruthenium Precursors for Direct Liquid Injection of Ruthenium and Ruthenium Oxide and Method of Using Same
Patent:
6,541,067 →
Application:
09/506,962 →
Composition and Method of Formation and Use Therefor in Chemical-Mechanical Polishing
Energy Beam Patterning of Protective Layers for Semiconductor Devices
Patent:
6,544,902 →
Application:
09/652,340 →
Graded Layer for Use in Semiconductor Circuits and Method for Making Same
Forming Sidewall Oxide Layers for Trench Isolation
Patent:
6,548,372 →
Application:
09/685,531 →
Reference Voltage Generator Tolerant to Temperature Variations
Telephone Outlet for Implementing a Local Area Network Over Telephone Lines and a Local Area Network Using Such Outlets
Patent:
6,549,616 →
Application:
09/531,692 →
Stereolithographic Method and Apparatus for Packaging Electronic Components and Resulting Structures
Patent:
6,549,821 →
Application:
09/259,142 →
Integrated Decoupling Capacitors
Nonvolatile Semiconductor Memory Device Having Changeable Spare Memory Address
Method for Efficient Analysis Semiconductor Failures
Patent:
6,553,521 →
Application:
09/511,169 →
Semiconductor Memory Device Incorporating Therein Ruthenium Electrode and Method for the Manufacture Thereof
Semiconductor Circuit Constructions, Capacitor Constructions, and Methods of Forming Semiconductor Circuit Constructions and Capacitor Constructions
Patent:
6,555,863 →
Application:
09/566,673 →
System and Method for Multilevel Dram Sensing and Restoring
Delay Locked Loop for Use in Semiconductor Memory Device
System for Testing Fast Synchronous Semiconductor Circuits
Removal of Photoresist Through the Use of Hot Deionized Water Bath, Water Vapor and Ozone Gas
Patent:
6,558,477 →
Application:
09/688,757 →
Apparatus and Method for Patterning a Semiconductor Wafer
Programmable Interconnect for Semiconductor Devices
Patent:
6,559,544 →
Application:
10/107,821 →
Dual Control Analog Delay Element
Memory Cell Decoder Not Including a Charge Pump
Method and Telephone Outlet for Allowing Telephone and Data Equipment to Be Connected to a Telephone Line via a Common Connector
Patent:
6,560,319 →
Application:
09/764,342 →
Method and Structure for Reducing Noise Effects in Content Addressable Memories
Patent:
6,563,727 →
Application:
10/208,011 →
Orthogonal Frequency Division Multiplexing System with Selectable Rate
Patent:
6,563,786 →
Application:
09/224,695 →
Method of Forming Contact Holes in Semiconductor Devices and Method of Forming Capacitors Using the Same
Integrated Circuit Chip Having Anti-Moisture-Absorption Film at Edge Thereof and Method of Forming Anti-Moisture-Absorption Film
Patent:
6,566,735 →
Application:
09/715,372 →
Integrated Circuitry and Dram Circuitry
Patent:
6,570,204 →
Application:
09/654,297 →
Memory System Capable of Increasing Utilization Efficiency of Semiconductor Memory Device and Method of Refreshing the Semiconductor Memory Device
Device and Method for Repairing a Semiconductor Memory
Dry Low K Film Application for Interlevel Dielectric and Method of Cleaning Etched Features
Patent:
6,573,175 →
Application:
09/998,729 →
Pecvd Method of Forming a Tungsten Silicide Layer on a Polysilicon Layer
Apparatus and Method for Feature Edge Detection in Semiconductor Processing
Reduced Area Sense Amplifier Isolation Layout in a Dynamic Ram Architecture
Solvent Prewet and Method and Apparatus to Dispense the Solvent Prewet
Tungsten Layer Formation Method for Semiconductor Device and Semiconductor Device Using the Same
Patent:
6,579,794 →
Application:
09/357,126 →
Capacitor Electrode for Integrating High K Materials
Priority Encoder Circuit and Method for Content Addressable Memory
Nonvolatile Semiconductor Memory Device and Manufacturing Method Thereof
Transfer Circuit of Semiconductor Device and Structure Thereof
Low Power Content Addressable Memory Architecture
Patent:
6,584,003 →
Application:
10/134,753 →
Method of Forming Dual-Metal Gates in Semiconductor Device
Delay Locked Loop
Erase Block Architecture for Non-Volatile Memory
Patent:
6,587,383 →
Application:
10/100,856 →
Method and Apparatus for Reducing Latency in a Memory System
Method and Apparatus for Providing a Packet Buffer Random Access Memory
Patent:
6,590,901 →
Application:
09/283,778 →
Method of Forming a Metal Wiring in a Semiconductor Device with Copper Seed
Register Controlled Dll Reducing Current Consumption
Methods for Forming and Integrated Circuit Structures Containing Ruthenium and Tungsten Containing Layers
Method for Forming Wire in Semiconductor Device
Dilute Cleaning Composition and Method for Using Same
Self Refresh Circuit for Semiconductor Memory Device
Apparatus and Method for Operation of Multi-Bank Semiconductor Memory Device with an Up/Down Counter
Reduced Area Sense Amplifier Isolation Layout in a Dynamic Ram Architecture
Duty Cycle Correction Circuit
Low K Film Application for Interlevel Dielectric and Method of Cleaning Etched Features
Method of Making Memory Cell Arrays
Patent:
6,607,944 →
Application:
09/918,345 →
Selective Method to Form Roughened Silicon
Bitline Precharge
Efficient Digital Itu-Compliant Zero-Buffering Dtmf Detection Using the Non-Uniform Discrete Fourier Transform
Process for Fabricating Rusixoy-Containing Adhesion Layers
Sequential Pulse Deposition
Measurement Probe for Detecting Electrical Signals in an Integrated Semiconductor Circuit
Tester Apparatus for Electronic Components
A Capacitor Having Rusixoy-Containing Adhesion Layers
Integrated Circuit Devices Having Contact and Container Structures
Apparatus and System for Removing Photoresist Through the Use of Hot Deionized Water Bath, Water Vapor and Ozone Gas
Method of Forming Low Dielectric Silicon Oxynitride Spacer Films Highly Selective to Etchants
Method of Forming T-Shaped Isolation Layer, Method of Forming Elevated Salicide Source/Drain Region Using the Same, and Semiconductor Device Having T-Shaped Isolation Layer
Apparatus and Method for Feature Edge Detection in Semiconductor Processing
Patent:
6,624,897 →
Application:
09/292,396 →
Multilevel Dram Sensing Analog-to-Digital Converter
Capacitor Constructions
Paralleled Content Addressable Memory Search Engine
Reduction of Surface Roughness During Chemical Mechanical Planarization (Cmp)
Localized Array Threshold Voltage Implant to Enhance Charge Storage Within Dram Memory Cells
Method and Apparatus for Searching a Filtering Database with One Search Operation
Patent:
6,633,567 →
Application:
09/652,196 →
Methods and Solutions for Cleaning Polished Aluminum-Containing Layers, Methods for Making Metallization Structures, and the Structures Resulting from These Methods
Methods of Forming Semiconductor Circuit Constructions and Capacitor Constructions
Dram Cell Constructions
Cmos of Semiconductor Device and Method for Manufacturing the Same
Semiconductor Device Having Trench Isolation Structure and Method of Forming Same
Method of Forming Drams, Methods of Forming Access Transistors for Dram Devices, and Methods of Forming Transistor Source/Drain Regions
Delivery of Dissolved Ozone
Chemical Vapor Deposition of Titanium from Titanium Tetrachloride and Hydrocarbon Reactants
Solutions of Metal-Comprising Materials, and Methods of Making Solutions of Metal-Comprising Materials
Delayed Locked Loop Implementation in a Synchronous Dynamic Random Access Memory
Delayed Locked Loop Implementation in a Synchronous Dynamic Random Access Memory
Circuit for Generating Internal Address in Semiconductor Memory Device
Capacitor of an Integrated Circuit Device and Method of Manufacturing the Same
Method and Apparatus for Generating Forward Overrides in a Packet Switch
Patent:
6,661,791 →
Application:
09/473,074 →
Error Screening Based on Code and Control Information Consistency in a Communication System
Patent:
6,662,339 →
Application:
09/464,042 →
Gate Structure with High K Dielectric
Method and Apparatus for Selecting an Encryption Integrated Circuit Operating Mode
Column Redundancy for Content Addressable Memory
Methods of Forming Field Effect Transistors and Related Field Effect Transistor Constructions
Double Layer Electrode and Barrier System on Hemispherical Grain Silicon for Use with High Dielectric Constant Materials and Methods for Fabricating the Same
Test Apparatus for Parallel Testing a Number of Electronic Components and a Method for Calibrating the Test Apparatus
Integrated Circuitry Fuse Forming Methods, Integrated Circuitry Programming Methods, and Related Integrated Circuitry
Top Electrode in a Strongly Oxidizing Environment
Patent:
6,682,969 →
Application:
09/652,863 →
Methods of Forming Materials Comprising Tungsten and Nitrogen
Method of Making a Concave Capacitor
Patent:
6,682,984 →
Application:
09/535,483 →
Dynamic Memory Based on Single Electron Storage
Process, Voltage, Temperature Independent Switched Delay Compensation Scheme
Delay Circuit of Clock Synchronization Device Using Delay Cells Having Wide Delay Range
Detection Devices, Methods and Systems for Gas Phase Materials
Network for Telephony and Data Communication
Patent:
6,690,677 →
Application:
09/357,379 →
Method for Improved Processing and Etchback of a Container Capacitor
Deadhesion Method and Mechanism for Wafer Processing
Integrated Circuit Chip Having Anti-Moisture-Absorption Film at Edge Thereof and Method of Forming Anti-Moisture-Absorption Film
Barrier-Metal-Free Copper Damascene Technology Using Atomic Hydrogen Enhanced Reflow
System for Transmitting Messages to Improved Stations, and Corresponding Processing
Patent:
6,697,379 →
Application:
09/312,486 →
Method and Apparatus for Reducing Interference in Non-Stationary Subscriber Radio Units Using Flexible Beam Selection
Patent:
6,701,165 →
Application:
09/598,057 →
Method for Determining the Transit Time of Electrical Signals on Printed Circuit Boards Using Automatic Standard Test Equipment
Dual Match-Line, Twin-Cell, Binary-Ternary Cam
Method for Improving Thermal Process Steps
Patent:
6,706,616 →
Application:
09/914,749 →
Dram Cell Constructions
Pseudo Variable Resistor for Tester Platform
Method and Circuit for Accelerating Redundant Address Matching
Reduced Aspect Ratio Digit Line Contact Process Flow Used During the Formation of a Semiconductor Device
High Speed Dram Architecture with Uniform Access Latency
Method and Apparatus for an Interleaved Non-Blocking Packet Buffer
Patent:
6,711,170 →
Application:
09/386,589 →
Reticle Cleaning Without Damaging Pellicle
Circuit and Method for Testing a Memory Device
A Method of Forming Flow-Fill Structures
Patent:
6,716,077 →
Application:
09/572,079 →
Polishing Systems, Methods of Polishing Substrates, and Methods of Preparing Liquids for Semiconductor Fabrication Processes
Patent:
6,716,802 →
Application:
09/298,160 →
Aluminum-Beryllium Alloys for Air Bridges
Matchline Sensing for Content Addressable Memories
Polishing Systems, Methods of Polishing Substrates, and Methods of Cleaning Polishing Slurry from Substrate Surfaces
Method of Calibrating a Test System for Semiconductor Components, and Test Substrate
Erase Block Architecture for Non-Volatile Memory
Needle Comb Reticle Pattern for Critical Dimension and Registration Measurements Using a Registration Tool and Methods for Using Same
Dynamic Memory Based on Single Electron Storage
Carburized Silicon Gate Insulators for Integrated Circuits
Patent:
6,731,531 →
Application:
09/650,553 →
Non-Volatile Semiconductor Memory Device Having Shared Row Selection Circuit
Integrated Dynamic Memory and Operating Method
Methods of Forming Dram Cells
Method of Manufacturing a Capacitor Having Rusixoy-Containing Adhesion Layers
Methods to Form Rhodium-Rich Oxygen Barriers
Capacitor Structure
Damascene Capacitor Formed in Metal Interconnection Layer
Searchline Control Circuit and Power Reduction Method
Demonstration Control Adjunct Device for Printers
Patent:
6,747,752 →
Application:
09/187,267 →
Continuous Good Step Coverage Cvd Platinum Metal Deposition
Patent:
6,750,110 →
Application:
09/121,528 →
Capacitor Electrode for Integrating High K Materials
Patent:
6,750,500 →
Application:
09/225,887 →
Apparatus for Testing Semiconductor Devices
Laser Selection of Ions for Sputter Deposition of Titanium Containing Films
Patent:
6,752,912 →
Application:
09/384,740 →
Method and Apparatus for Wire Speed Ip Multicast Forwarding
Patent:
6,754,211 →
Application:
09/453,344 →
Method for Fabricating Capacitors in Semiconductor Devices
System for Testing Integrated Circuit Devices
Telephone Outlet for Implementing a Local Area Network Over Telephone Lines and a Local Area Network Using Such Outlets
Solvent Prewet and Method and Apparatus to Dispense the Solvent Prewet
Delivery of Dissolved Ozone
Patent:
6,758,938 →
Application:
09/386,247 →
Platinum-Rhodium Stack as an Oxygen Barrier in an Integrated Circuit Capacitor
Wiring Structure of Semiconductor Device
Low Power Semiconductor Memory Device Having a Normal Mode and a Partial Array Self Refresh Mode
Method of Forming a Capacitor and a Capacitor Construction
Barrier-Metal-Free Copper Damascene Technology Using Atomic Hydrogen Enhanced Reflow
Test Configuration and Test Method for Testing a Plurality of Integrated Circuits in Parallel
Process for Fabricating Rusixoy-Containing Adhesion Layers
Link Aggregation
Patent:
6,765,866 →
Application:
09/516,001 →
Method and Apparatus for Integrated Circuit Design with a Software Tool
Semiconductor Device Having a Metal Insulator Metal Capacitor
Cmos of Semiconductor Device and Method for Manufacturing the Same
Non-Volatile Semiconductor Memory Device
Fast Aging Scheme for Search Engine Databases Using a Linear Feedback Shift Register
Semiconductor Memory Asynchronous Pipeline
Solutions of Metal-Comprising Materials
Method for Releasable Contact-Connection of a Plurality of Integrated Semiconductor Modules on a Wafer
Thermal Processing of Metal Alloys for an Improved Cmp Process in Integrated Circuit Fabricatin
Chemical Treatment of Semiconductor Substrates
Low Dielectric Silicon Oxynitride Spacer Films and Devices Incorporating Such Films
Gapped-Plate Capacitor
Content Addressable Memory Architecture
Semiconductor Device Having No Cracks in One or More Layers Underlying a Metal Line Layer and Method of Manufacturing the Same
High Bandwidth Memory Interface
Semiconductor Circuit Constructions,Capacitor Constructions, and Methods of Forming Semiconductor Circuit Constructions and Capacitor Constructions
Rhodium-Rich Integrated Circuit Capacitor Electrode
Circuit for Testing an Integrated Circuit
Thermal Processing of Metal Alloys for an Improved Cmp Process in Integrated Circuit Fabrication
Circuit Configuration for Selectively Transmitting Information Items from a Measuring Device to Chips on a Wafer During Chip Fabrication
Method and Apparatus for Accelerating Signal Equalization Between a Pair of Signal Lines
Method for Producing Water for Use in Manufacturing Semiconductors
Capacitor Structure
Reticle Cleaning Without Damaging Pellicle
Metal Local Interconnect Self-Aligned Source Flash Cell
Method for Controlling Radiation Beam Intensity Directed to Microlithographic Substrates
Carburized Silicon Gate Insulators for Integrated Circuits
Patent:
6,794,255 →
Application:
09/258,467 →
Reducing Asymmetrically Deposited Film Induced Registration Error
Method and Apparatus Including Reverse Play of a Multiplexed Packet Data Stream
Localized Array Threshold Voltage Implant Enhance Charge Storage Within Dram Memory Cells
Patent:
6,800,520 →
Application:
10/234,576 →
Method of Forming a Metal Oxide Film
Rusixoy-Containing Adhesion Layers
Microlithographic Device, Microlithographic Assist Features, System for Forming Contacts and Other Structures, and Method of Determining Mask Patterns
Arrayed Processing Element Redundancy Architecture
Method of Forming Integrated Circuitry, and Method of Forming a Contact Opening
Bi-Directional Amplifier and Method for Accelerated Bus Line Communication
Method for Improved Processing and Etchback of a Container Capacitor
Capacitor of an Integrated Circuit Device and Method of Manufacturing the Same
Integrated Decoupling Capacitors
Memory Structure with an Annealed Film
Localized Array Threshold Voltage Implant to Enhance Charge Storage Within Dram Memory Cells
Method of Manufacturing a Contact Plug for a Semiconductor Device
Sram-Compatible Memory Device Employing Dram Cells
Enhanced Collimated Deposition
Patent:
6,827,824 →
Application:
08/631,465 →
Method for Fabricating a Capacitor of a Semiconductor Device and a Capacitor Made Thereby
Methods for Forming and Integrated Circuit Structures Containing Ruthenium and Tungsten Containing Layers
Antifuse Structure and Method of Use
Patent:
6,836,000 →
Application:
09/515,760 →
Measurement of Packet Loss Ratio in a Network Using End-Point Data
Method and Apparatus for Design of Integrated Circuits
Solvated Ruthenium Precursors for Direct Liquid Injection of Ruthenium and Ruthenium Oxide
Dilute Cleaning Composition and Method for Using Same
Network Combining Wired and Non-Wired Segments
Patent:
6,842,459 →
Application:
09/552,564 →
Methods of Forming Capacitors and Resultant Capacitor Structures
Method for Forming Contact Plug in Semiconductor Device
Solvated Ruthenium Precursors for Direct Liquid Injection of Ruthenium and Ruthenium Oxide
Synchronous Sram-Compatible Memory and Method of Driving the Same
Temperature-Dependent Refresh Cycle for Dram
Reducing Asymmetrically Deposited Film Induced Registration Error
Method and Probe Card Configuration for Testing a Plurality of Integrated Circuits in Parallel
Timing Vernier Using a Delay Locked Loop
Method for Fabricating Metal-Oxide Semiconductor Transistor
Semiconductor Chip Package and Method of Fabricating Same
Method and Apparatus for Providing Input Back Pressure in an Output Buffered Switch
Patent:
6,856,595 →
Application:
09/574,621 →
Method and Apparatus for the Fabrication of Ferroelectric Films
Processes to Form a Metallic Film Stack
Nanotube Semiconductor Devices and Methods for Making the Same
Duty Cycle Correction Circuit and Delay Locked Loop Having the Same
Apparatus and Method of Compensating for Phase Delay in Semiconductor Device
Method for Removing Organic Material from a Substrate and for Oxidizing Oxidizable Material Thereon
Continuous Good Step Coverage Cvd Platinum Metal Deposition
Device Addressing Gas Contamination in a Wet Process
Process for Fabricating Rusixoy-Containing Adhesion Layers
Capacitor Having Rusixoy-Containing Adhesion Layers
Content Addressable Memory Cell Having Improved Layout
Method and Apparatus for Synchronization of Row and Column Access Operations
Solvent Prewet and Method to Dispense the Solvent Prewet
Methods of Forming Iintegrated Circuit Devices Having a Metal-Insulator-Metal (Mim) Capacitor
Recessed Gate Electrode Mos Transistors Having a Substantially Uniform Channel Length Across a Width of the Recessed Gate Electrode and Methods of Forming Same
Capacitor Structure
Content Addressable Memory Cell
Method and Apparatus for Replacing Defective Rows in a Semiconductor Memory Array
Low K Film Application for Interlevel Dielectric and Method of Cleaning Etched Features
High Speed Dram Architecture with Uniform Access Latency
Method and Apparatus for Accelerating Retrieval of Data from a Memory System with Cache by Reducing Latency
Method for Repairing a Semiconductor Memory
Refresh Control Circuit and Method for Semiconductor Memory Device
Synchronous Dram with Selectable Internal Prefetch Size
Capacitor Constructions
Patent:
6,900,496 →
Application:
08/886,388 →
Mixed Composition Interface Layer and Method of Forming
Stereolithographic Method and Apparatus for Packaging Electronic Components
Device and Method for Repairing a Semiconductor Memory
Methods for Stereolithographic Processing of Components and Assemblies
System for Depositing a Layered Film
Cvd of Ptrh with Good Adhesion and Morphology
Semiconductor Memory Device with Modified Global Input/Output Scheme
Detection Devices, Methods and Systems for Gas Phase Materials
Capacitor of an Integrated Circuit Device and Method of Manufacturing the Same
Adapter for Mounting a Faceplate of a First Style on to an Electrical Outlet Cavity of a Second Style
Patent:
6,927,340 →
Application:
10/451,544 →
System for Testing Integrated Circuit Devices
High Voltage Supply Circuit and a Method of Supplying High Voltage
Method and Systems for Bandwidth Management in Packet Data Networks
System and Method for Transmission-Line Termination by Signal Cancellation, and Applications Thereof
Determining the Position of a Constant Frequency Interval in a Telecommunication Signal
Patent:
6,937,672 →
Application:
09/515,224 →
Methods and Apparatus for Duty Cycle Control
Aluminum-Beryllium Alloys for Air Bridges
Delay Locked Loop and Locking Method Thereof
Patent:
6,943,602 →
Application:
11/026,970 →
Delay Model Circuit for Use in Delay Locked Loop
Local Area Network for Distributing Data Communication, Sensing and Control Signals
Patent:
6,956,826 →
Application:
09/349,020 →
Gapped-Plate Capacitor
Method and System for Packet Encryption
Telephone Communication System and Method Over Local Area Network Wiring
Patent:
6,961,303 →
Application:
09/666,856 →
Method of Fabricating Dielectric Layer
Method of Forming Flow-Fill Structures
Methods of Forming Nitrogen-Containing Masses, Silicon Nitride Layers, and Capacitor Constructions
Cascaded Charge Pump Power Supply
Apparatus for the Automated Testing, Calibration and Characterization of Test Adapters
Networks for Telephony and Data Communication
Apparatus for Flexible Deactivation of Word Lines of Dynamic Memory Modules and Method Therefor
Chemical Vapor Deposition of Titanium from Titanium Tetrachloride and Hydrocarbon Reactants
Synchronous Dram with Selectable Internal Prefetch Size
Data Output Control Circuit
Matchline Sense Circuit and Method
Sorting Method and Apparatus Using a Cam
Delay locked loop implementation in a synchronous dynamic random access memory
Frequency Division Multiplexing System with Selectable Rate
Content Addressable Memory Architecture
Method of Repairing a Failed Wordline
An Apparatus for the in Situ Alignment of a Mask and a Semiconductor Wafer.
Mismatch-Dependent Power Allocation Technique for Match-Line Sensing in Content-Addressable Memories
Local Area Network of Serial Intelligent Cells
Method and Apparatus for Reducing Pool Starvation in a Shared Memory Switch
Patent:
7,007,071 →
Application:
09/624,276 →
Microlithographic Mask Structures and Method of Fabrication
Chemical Treatment of Semiconductor Substrates
Structures and Methods for Enhancing Capacitors in Integrated Circuits
Patent:
7,009,240 →
Application:
09/598,355 →
Method and Apparatus for Selecting an Encryption Integrated Circuit Operating Mode
Synchronization Circuit and Method with Transparent Latches
Method and Apparatus for Depositing Films
Semiconductor Constructions
High Speed Dram Architecture with Uniform Access Latency
Reduced Aspect Ratio Digit Line Contact Process Flow Used During the Formation of a Semiconductor Device
Local Area Network of Serial Intelligent Cells
Method of Manufacturing Semiconductor Devices
Top Electrode in a Strongly Oxidizing Environment
Method and Device for Robust Fallback in Data Communication Systems
Apparatus for Producing Water for Use in Manufacturing Semiconductors
Temperature-Dependent Dram Self-Refresh Circuit
Local Area Network of Serial Intellegent Cells
Integrated Circuits with Rhodium-Rich Structures
Timing Vernier Using a Delay Locked Loop
Flash Memory Device with Improved Programming Performance
Process for the Fabrication of Oxide Films
Method and Apparatus for Synchronization of Row and Column Access Operations
Write Circuit of Double Data Rate Synchronous Dram
Cascading Content Addressable Memory Devices with Programmable Input / Output Connections
Memory Cell Arrays
Method and Apparatus for Controlling Radiation Beam Intensity Directed to Microlithographic Substrates
Managing Power on Integrated Circuits Using Power Islands
Method and Apparatus for Integrated Circuit Design with Library Cells
Dielectric Material Forming Methods and Enhanced Dielectric Materials
Dynamic Linking of Banks in Configurable Content Addressable Memory Systems
Semiconductor Processing Methods
Semiconductor Memory Device with Efficient Multiplexing of I/O Pad in Multi-Chip Package
Data Path Having Grounded Precharge Operation and Test Compression Capability
Method and Apparatus for Interconnecting Content Addressable Memory Devices
System for Transmission Line Termination by Signal Cancellation
Semiconductor Memory Device Having Row Path Control Circuit and Operating Method Thereof
Method for Producing Water for Use in Manufacturing Semiconductors
Capacitor of an Integrated Circuit Device and Method of Manufacturing the Same
Antifuse Structure and Method of Use
Redundancy Circuit in Semiconductor Memory Device Having a Multiblock Structure
Nanotube Semiconductor Devices and Methods for Making the Same
Demonstration Control Adjunct Device for Printers
Non-Volatile Semiconductor Memory Device Having Sense Amplifier with Increased Speed
Circuit and Method of Generating a Boosted Voltage
Delay Stage Insensitive to Operating Voltage and Delay Circuit Including the Same
Data Driving Circuit and Semiconductor Memory Device Having the Same
Circuit, System and Method for Selectively Turning Off Internal Clock Drivers
Main Amplifier and Semiconductor Device
Local Area Network of Serial Intelligent Cells
Fixed Offset Digital-to-Analog Conversion Device and Method
Semiconductor Memory Device
Method for Forming Conductive Line of Semiconductor Device
Cleaning Solution and Cleaning Method of a Semiconductor Device
Dram Constructions and Dram Devices
Telephone Communication System Over a Single Telephone Line
Patent:
7,106,721 →
Application:
09/594,765 →
Adapter for Mounting a Faceplate of a First Style on to an Electrical Outlet Cavity of a Second Style
Method and Apparatus for Optimizing Performance and Battery Life of Electronic Devices Based on System and Application Parameters
Patent:
7,111,179 →
Application:
10/268,914 →
Nonvolatile Semiconductor Memory Device with Scalable Two Transistor Memory Cells
Flow-Fill Structures
Frequency-Doubling Delay Locked Loop
Method for Forming Polysilicon Plug of Semiconductor Device
Duty Cycle Correction Circuit of Delay Locked Loop and Delay Locked Loop Having the Duty Cycle Correction Circuit
Ternary Cam Cell for Reduced Matchline Capacitance
Flash Memory Device with Improved Programming Performance
Synchronous Dram with Selectable Internal Prefetch Size
Clock Logic Domino Circuits for High-Speed and Energy Efficient Microprocessor Pipelines
Contiguous Block Addressing Scheme
Telephone Outlet for Implementing a Local Area Network Over Telephone Lines and a Local Area Network Using Such Outlets
Sorting Method and Apparatus Using a Cam
Reducing Asymmetrically Deposited Film Induced Registration Error
Timing Vernier Using a Delay Locked Loop
Method of Inhibiting Degradation of Gate Oxide Film
Input Signal Receiving Device of Semiconductor Memory Unit
Semiconductor Memory Device for Low Power System
Gapped-Plate Capacitor
Contiguous Block Addressing Scheme
Contiguous Block Addressing Scheme
Contiguous Block Addressing Scheme
Semiconductor Memory Device for Simultaneously Testing Blocks of Cells
Method of Forming a Metal Gate in a Semiconductor Device Using Atomic Layer Deposition Process
Dielectric Material Forming Methods and Enhanced Dielectric Materials
Semiconductor Memory Device with Cylindrical Storage Electrode and Method of Manufacturing the Same
Data Path Having Grounded Precharge Operation and Test Compression Capability
Memory Apparatus Having Multi-Port Architecture for Supporting Multi Processor
Method for Forming Raised Structures by Controlled Selective Epitaxial Growth of Facet Using Spacer
Etching Method in a Semiconductor Processing and Etching System for Performing the Same
High Output Impedance Charge Pump for Pll/Dll
Multi-Level High Voltage Generator
Semiconductor Memory Asynchronous Pipeline
Flash Memory Device Capable of Preventing Program Disturbance According to Partial Programming
Barrier-Metal-Free Copper Damascene Technology Using Atomic Hydrogen Enhanced Reflow
Semiconductor Devices Having a Pocket Line and Methods of Fabricating the Same
Local Area Network of Serial Intelligent Cells
Block Programmable Priority Encoder in a Cam
Method and Apparatus for Initializing a Delay Locked Loop
Voltage Regulating Circuit and Method of Regulating Voltage
Adapter for Mounting a Faceplate of a First Style to an Electrical Outlet Cavity of a Second Style
Packet Addressing Programmable Dual Port Memory Devices and Related Methods
On Die Termination Mode Transfer Circuit in Semiconductor Memory Device and Its Method
Telephone Communication System Over a Single Telephone Line
Duty Cycle Correction Circuit for Use in a Semiconductor Device
Local Area Network for Distributing Data Communication, Sensing and Control Signals
Differential Type Delay Cells and Methods of Operating the Same
High Voltage Generator Circuit with Ripple Stabilization Function
Cleaning Solution and Cleaning Method of a Semiconductor Device
Method of Forming a Metal Oxide Film
Local Area Network of Serial Intelligent Cells
Circuit and Method for Generating Wordline Voltage in Nonvolatile Semiconductor Memory Device
Low Leakage and Data Retention Circuitry
Mismatch-Dependent Power Allocation Technique for Match-Line Sensing in Content-Addressable Memories
Method and Apparatus for Controlling Radiation Beam Intensity Directed to Microlithograhic Substrates
Structures and Methods for Enhancing Capacitors in Integrated Circuits
Semiconductor Device Having No Cracks in One or More Layers Underlying a Metal Line Layer and Method of Manufacturing the Same
Memory Chip Architecture Having Non-Rectangular Memory Banks and Method for Arranging Memory Banks
Port Packet Queuing
Patent:
7,236,489 →
Application:
09/559,190 →
Methods of Forming Semiconductor Constructions
System and Method for Selectively Increasing Surface Temperature of an Object
Voltage Down Converter for High Speed Memory
Matchline Sense Circuit and Method
Methods for Forming and Integrated Circuit Structures Containing Ruthenium and Tungsten Containing Layers
Patent:
7,253,076 →
Application:
09/590,795 →
Dual Control Analog Delay Element and Related Delay Method
Error Correction Scheme for Memory
Chemical Vapor Deposition of Titanium from Titanium Tetrachloride and Hydrocarbon Reactants
Method and Apparatus for Simultaneous Differential Data Sensing and Capture in a High Speed Memory
Telephone Communication System Over a Single Telephone Line
Apparatus for Stereolithographic Processing of Components and Assemblies
Method for Manufacturing Semiconductor Device
Method and Apparatus for Synchronization of Row and Column Access Operations
Method and Apparatus for Reordering Entries in a Multi Probe Lookup
Systems and Methods for Minimizing Static Leakage of an Integrated Circuit
Flash Memory Device with Improved Programming Performance
Delay Locked Loop Circuit and Method
Dynamic Random Access Memory Device and Method for Self-Refreshing Memory Cells with Temperature Compensated Self-Refresh
Method and System for Design and Routing in Transparent Optical Networks
Integrated Circuitry
Semiconductor Integrated Circuit Having Current Leakage Reduction Scheme
Local Area Network of Serial Intellegent Cells
High Bandwidth Memory Interface
Method and Apparatus for Searching a Filtering Database with One Search Operation
Compare Circuit for a Content Addressable Memory Cell
Etching Method in a Semiconductor Processing and Etching System for Performing the Same
Voltage Level Shifter Circuit
Trunking in a Matrix
Chemical Treatment of Semiconductor Substrates
Method for Fabricating Semiconductor Device
Method and System for Providing Dc Power on Local Telephone Lines
Method and Apparatus for Accelerating Retrieval of Data from a Memory System with Cache by Reducing Latency
Trench Isolation Method with an Epitaxially Grown Capping Layer
Method of Forming an Interconnection Line in a Semiconductor Device
System for Transmission Line Termination by Signal Cancellation
Non-Volatile Memory Device with Page Buffer Having Dual Registers and Methods Using the Same
Wide Frequency Range Delay Locked Loop
Adapter for Mounting a Faceplate of a First Style to an Electrical Outlet Cavity of a Second Style
Semiconductor Device and Method for Fabricating a Semiconductor Device
Low Leakage and Data Retention Circuitry
Process, Voltage, Temperature Independent Switched Delay Compensation Scheme
Method of Manufacturing Semiconductor Device
Etching Solution for Silicon Oxide and Method of Manufacturing a Semiconductor Device Using the Same
Link Aggregation
Method and Apparatus for Performing Repeated Content Addressable Memory Searches
Methods for Programming and Reading Nand Flash Memory Device and Page Buffer Performing the Same
Apparatus and Method for Self-Refreshing Dynamic Random Access Memory Cells
Dynamic Random Access Memory Device and Method for Self-Refreshing Memory Cells
On-Die Termination Apparatus
Semiconductor Memory Device
Systems and Methods for Minimizing Static Leakage of an Integrated Circuit
Matchline Sense Circuit and Method
Method for Detecting Column Fail by Controlling Sense Amplifier of Memory Device
Semiconductor Integrated Circuit Having Low Power Consumption with Self-Refresh
Method for allocating processor resources and system for encrypting data
Methods for Enhancing Capacitors in Integrated Circuits
Timing Vernier Using a Delay Locked Loop
Method for Fabricating Semiconductor Device Having Capacitor
Telephone Communication System Over a Single Telephone Line
Method and Apparatus for Reducing Pool Starvation in a Shared Memory Switch
Charge Pump for Pll/Dll
Method for Forming Storage Node of Capacitor in Semiconductor Device
Data Input Circuit of Semiconductor Memory Device and Data Input Method Thereof
Power Managers for an Integrated Circuit
Local Area Network of Serial Intelligent Cells
Semiconductor Memory Device Sharing a Data Line Sense Amplifier and a Write Driver in Order to Reduce a Chip Size
Semiconductor Device and Method for Fabricating the Same
Pmos Transistor of Semiconductor Device, Semiconductor Device Comprising the Same, and Method for Manufacturing the Same
Outlet with Analog Signal Adapter, a Method for Use Thereof and a Network Using Said Outlet
Low Leakage and Data Retention Circuitry
Telephone Communication System and Method Over Local Area Network Wiring
Method for Manufacturing Semiconductor Device
Self Refresh Oscillator and Oscillation Signal Generation Method of the Same
High Speed Dram Architecture with Uniform Access Latency
Semiconductor Memory Device
System for Transmission Line Termination by Signal Cancellation
Outlet with Analog Signal Adapter, a Method for Use Thereof and a Network Using Said Outlet
Frequency-Doubling Delay Locked Loop
Method for Fabricating a Semiconductor Device
Phase Detector Circuit and Method Therefor
Telephone Communication System Over a Single Telephone Line
Method for Repairing a Semiconductor Memory
Start Up Circuit for Delay Locked Loop
Method and Apparatus for Interconnecting Content Addressable Memory Devices
Transistor of Semiconductor Memory Device
Telephone Communication System and Method Over Local Area Network Wiring
Network for Telephony and Data Communication
Sorting Method and Apparatus Using a Cam
Semiconductor Memory Device and Driving Method Thereof
Telephone Communication System and Method Over Local Area Network Wiring
Dynamic Random Access Memory with Fully Independent Partial Array Refresh Function
Apparatus and Method for Self-Refreshing Dynamic Random Access Memory Cells
Network for Telephony and Data Communication
On-Die Termination Circuit and Driving Method Thereof
Dynamic Random Access Memory Device and Method for Self-Refreshing Memory Cells with Temperature Compensated Self-Refresh
Semiconductor Devices Having a Pocket Line and Methods of Fabricating the Same
Content Addressable Memory Architecture
Method and Apparatus for Synchronization of Row and Column Access Operations
Integrated Circuit with Signal Bus Formed by Cell Abutment of Logic Cells
Circuit and Method for Testing Multi-Device Systems
Semiconductor Memory Asynchronous Pipeline
Low Power Match-Line Sensing Circuit
Flash Memory Program Inhibit Scheme
Memory with Output Control
Device, Method and System for Estimating the Termination to a Wired Transmission-Line Based on Determination of Characteristic Impedance
Addressable Outlet, and a Network Using Same
Network for Telephony and Data Communication
Telephone Outlet for Implementing a Local Area Network Over Telephone Lines and a Local Area Network Using Such Outlets
Memory System and Method with Serial and Parallel Modes
Voltage Level Shifter Circuit
Circuit and Method for Glitch Correction
Telephone Outlet with Packet Telephony Adapter, and a Network Using Same
Non-Volatile Memory Devices and Control and Operation Thereof
Five Channel Fin Transistor and Method for Fabricating the Same
Phase Shifting in Dll/Pll
Non-Volatile Semiconductor Memory with Page Erase
Hybrid Solid-State Memory System Having Volatile and Non-Volatile Memory
Low Power Memory Architecture
Compare Circuit for a Content Addressable Memory Cell
Cleaning Solution and Cleaning Method of a Semiconductor Device
Phase-Locked Loop Filter Capacitance with a Drag Current
Multi-Level Cell Access Buffer with Dual Function
Decoding Control with Address Transition Detection in Page Erase Function
Adapter for Mounting a Faceplate of a First Style to an Electrical Outlet Cavity of a Second Style
Low Leakage and Data Retention Circuitry
Flash Multi-Level Threshold Distribution Scheme
Voltage Down Converter for High Speed Memory
Telephone Communication System Over a Single Telephone Line
Synchronization Circuit and Method with Transparent Latches
Delay Locked Loop Implementation in a Synchronous Dynamic Random Access Memory
Power Up Circuit with Low Power Sleep Mode Operation
Barrier-Metal-Free Copper Damascene Technology Using Atomic Hydrogen Enhanced Reflow
Charge Pump for Pll/Dll
Temperature Detector in an Integrated Circuit
Method and System for Packet Encryption
Network Combining Wired and Non-Wired Segments
Network Combining Wired and Non Wired Segments
Error Correction Scheme for Memory
Semiconductor Integrated Circuit Having Current Leakage Reduction Scheme
Non-Volatile Semiconductor Memory Having Multiple External Power Supplies
Systems and Methods for Minimizing Static Leakage of an Integrated Circuit
Method and Apparatus for Synchronization of Row and Column Access Operations
Non-Volatile Memory with Dynamic Multi-Mode Operation
Multiple Independent Serial Link Memory
Memory System Having Incorrupted Strobe Signals
Local Area Network of Serial Intelligent Cells
Delay Locked Loop Circuit
Telephone System Having Multiple Distinct Sources and Accessories Therefor
Start Up Circuit for Delay Locked Loop
Apparatus and Method for Interfacing to a Memory
Circuit, System and Method for Selectively Turning Off Internal Clock Drivers
Timing Vernier Using a Delay Locked Loop
Duty Cycle Correction Circuit of Delay Locked Loop and Delay Locked Loop Having the Duty Cycle Correction Circuit
Method and Apparatus for Providing a Packet Buffer Random Access Memory
Voltage Level Shifter and Buffer Using Same
Circuit and Method for Testing Multi-Device Systems
Telephone Outlet with Packet Telephony Adaptor, and a Network Using Same
Sram Leakage Reduction Circuit
Synchronous Memory Read Data Capture
Modular Outlet
Low Power Match-Line Sensing Circuit
Storage of Data in Memory via Packet Strobing
Modular Outlet
Modular Outlet
Charge Pump for Pll/Dll
Dynamic Random Access Memory Device and Method for Self-Refreshing Memory Cells with Temperature Compensated Self-Refresh
System for Transmission Line Termination by Signal Cancellation
Apparatus and Method for Self-Refreshing Dynamic Random Access Memory Cells
Method and System for Providing Dc Power on Local Telephone Lines
Simplified Bias Circuitry for Differential Buffer Stage with Symmetric Loads
Flash Memory Program Inhibit Scheme
Network Combining Wired and Non-Wired Segments
Telephone Outlet for Implementing a Local Area Network Over Telephone Lines and a Local Area Network Using Such Outlets
Flash Memory Device with Data Output Control
Flow-Fill Spacer Structures for Flat Panel Display Device
Mulitple-Bit Per Cell (Mbc) Non-Volatile Memory Apparatus and System Having Polarity Control and Method of Programming Same
Telephone System Having Multiple Sources and Accessories Therefor
Pulse Counter with Clock Edge Recovery
Method and Apparatus for Reducing Pool Starvation in a Shared Memory Switch
Frequency-Doubling Delay Locked Loop
Private Telephone Network Connected to More Than One Public Network
Independent Link and Bank Selection
Phase-Locked Loop Circuitry Using Charge Pumps with Current Mirror Circuitry
High Speed Dram Architecture with Uniform Access Latency
Semiconductor Device and Method for Selection and De-Selection of Memory Devices Interconnected in Series
Apparatus and Method for Communicating with Semiconductor Devices of a Serial Interconnection
Outlet Add-on Module
Asic Design Using Clock and Power Grid Standard Cell
Apparatuses for Synchronous Transfer of Information
Dynamic Random Access Memory Device and Method for Self-Refreshing Memory Cells
Telephone Outlet with Packet Telephony Adapter, and a Network Using Same
Apparatus and Method of Page Program Operation for Memory Devices with Mirror Back-Up of Data
Decoding Control with Address Transition Detection in Page Erase Function
Semiconductor Devices Having a Contact Plug and Fabrication Methods Thereof
Method for Forming Storage Node of Capacitor in Semiconductor Device
Method for Stacking Serially-Connected Integrated Circuits and Multi-Chip Device Made from Same
Data Flow Control in Multiple Independent Port
Flash Memory System Control Scheme
Partial Block Erase Architecture for Flash Memory
Port Packet Queuing
Nonvolatile Memory Having Non-Power of Two Memory Capacity
Non-Volatile Memory Serial Core Architecture
Method and Apparatus for Synchronization of Row and Column Access Operations
Apparatus and Method for Capturing Serial Input Data
Flash Multi-Level Threshold Distribution Scheme
Memory with Output Control
Adapter for Mounting a Faceplate of a First Style to an Electrical Outlet Cavity of a Second Style
Local Area Network of Serial Intelligent Cells
Congestion Level Management in a Network Device
Dynamic Impedance Control for Input/Output Buffers
Local Area Network for Distributing Data Communication, Sensing and Control Signals
Methods and Systems for Failure Isolation and Data Recovery in a Configuration of Series-Connected Semiconductor Devices
Power Supplies in Flash Memory Devices and Systems
Telephone Communication System and Method Over Local Area Network Wiring
Semiconductor Device Having No Cracks in One or More Layers Underlying a Metal Line Layer
On-Die Termination Circuit and Driving Method Thereof
Local Area Network of Serial Intelligent Cells
Apparatus and Method for Producing Identifiers Regardless of Mixed Device Type in a Serial Interconnection
Self Refresh Oscillator and Oscillation Signal Generation Method of the Same
Outlet with Analog Signal Adapter, a Method for Use Thereof and a Network Using Said Outlet
Semiconductor Device Having Metal Lines with Slits
Timing Vernier Using a Delay Locked Loop
Semiconductor Memory Asynchronous Pipeline
Methods and Apparatus for Clock Signal Synchronization in a Configuration of Series-Connected Semiconductor Devices
Modular Outlet
Phase-Locked Loop Circuitry Using Charge Pumps with Current Mirror Circuitry
Memory Device and Method for Repairing a Semiconductor Memory
Non-Volatile Semiconductor Memory with Page Erase
Outlet with Analog Signal Adapter, a Method for Use Thereof and a Network Using Said Outlet
Modular Outlet
Network Combining Wired and Non-Wired Segments
Outlet Add-on Module
Clock Mode Determination in a Memory System
Barrier-Metal-Free Copper Damascene Technology Using Atomic Hydrogen Enhanced Reflow
Single-Strobe Operation of Memory Devices
Memory System Having Incorrupted Strobe Signals
Outlet with Analog Signal Adapter, a Method for Use Thereof and a Network Using Said Outlet
Process, Voltage, Temperature Independent Switched Delay Compensation Scheme
Method and Apparatus for Traversing a Multiplexed Data Packet Stream
Delay Locked Loop Circuit
Charge Pump for Pll/Dll
Stacked Semiconductor Devices Including a Master Device
Pre-Charge Voltage Generation and Power Saving Modes
Modular Command Structure for Memory and Memory System
Dynamic Random Access Memory Device and Method for Self-Refreshing Memory Cells
Non-Volatile Memory Devices and Control and Operation Thereof
Apparatus and Method of Page Program Operation for Memory Devices with Mirror Back-Up of Data
Sequential Pulse Deposition
Circuit and Method for Testing Multi-Device Systems
Addressable Outlet, and a Network Using the Same
Data Channel Test Apparatus and Method Thereof
Circuit for Clamping Current in a Charge Pump
Dynamic Random Access Memory with Fully Independent Partial Array Refresh Function
Device, Method and System for Estimating the Termination to a Wired Transmission-Line Based on Determination of Characteristic Impedance
Method for Stacking Serially-Connected Integrated Circuits and Multi-Chip Device Made from Same
Hybrid Solid-State Memory System Having Volatile and Non-Volatile Memory
System and Method of Operating Memory Devices of Mixed Type
Temperature Detector in an Integrated Circuit
Network Combining Wired and Non-Wired Segments
Low Leakage and Data Retention Circuitry
Nand Flash Memory Having Multiple Cell Substrates
Independent Link and Bank Selection
Power Managers for an Integrated Circuit
Apparatus and Method for Modeling Coarse Stepsize Delay Element and Delay Locked Loop Using Same
Multiple Bit Per Cell Non Volatile Memory Apparatus and System Having Polarity Control and Method of Programming Same
Source Side Asymmetrical Precharge Programming Scheme
Outlet with Analog Signal Adapter, a Method for Use Thereof and a Network Using Said Outlet
Composite Memory Having a Bridging Device for Connecting Discrete Memory Devices to a System
Method and Apparatus for Synchronization of Row and Column Access Operations
Multi-Level Cell Access Buffer with Dual Function
Local Area Network of Serial Intelligent Cells
Local Area Network of Serial Intelligent Cells
Bias Generator Providing for Low Power, Self-Biased Delay Element and Delay Line
Hierarchical Common Source Line Structure in Nand Flash Memory
Local Area Network of Serial Intelligent Cells
Systems and Methods for Minimizing Static Leakage of an Integrated Circuit
Dual Function Compatible Non-Volatile Memory Device
Local Area Network of Serial Intelligent Cells
Addressable Outlet, and a Network Using the Same
Apparatus and Method for Identifying Device Types of Series-Connected Devices of Mixed Type
Non-Volatile Semiconductor Memory with Page Erase
Method and Apparatus for Reducing Pool Starvation in a Shared Memory Switch
Power Managers for an Integrated Circuit
Method and System for Accessing a Flash Memory Device
Telephone Communication System Over a Single Telephone Line
Wide Frequency Range Delay Locked Loop
Apparatus and Method for Producing Device Identifiers for Serially Interconnected Devices of Mixed Type
Apparatus and Method for Identifying Device Type of Serially Interconnected Devices
Timing Vernier Using a Delay Locked Loop
Flash Memory Program Inhibit Scheme
Integrated Circuit with Signal Bus Formed by Cell Abutment of Logic Cells
Hybrid Content Addressable Memory
Dynamic Impedance Control for Input/Output Buffers
Simplified Bias Circuitry for Differential Buffer Stage with Symmetric Loads
Device and Method for Transferring Data to a Non-Volatile Memory Device
Apparatus and Method for Self-Refreshing Dynamic Random Access Memory Cells
Non-Volatile Memory with Dynamic Multi-Mode Operation
High Speed Dram Architecture with Uniform Access Latency
Apparatus and Method for Using a Page Buffer of a Memory Device as a Temporary Cache
System for Transmission Line Termination by Signal Cancellation
Apparatus and Method of Page Program Operation for Memory Devices with Mirror Back-Up of Data
Termination Circuit for on-Die Termination
Dual Control Analog Delay Element
Power Supplies in Flash Memory Devices and Systems
Method and Apparatus for Reducing Power Consumption in Digital Electronic Circuits
Patent:
36,839 →
Application:
09/212,854 →
Method for Forming an Oxynitride Film in a Semiconductor Device
Patent:
37,960 →
Application:
08/824,879 →
Single Chip Frame Buffer and Graphics Accelerator
Patent:
40,326 →
Application:
10/264,013 →
Single Chip Frame Buffer and Graphics Accelerator
Patent:
41,565 →
Application:
11/872,353 →
Related Assignments
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Change of Address of Assignee
Apr 15, 2009
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Jan 10, 2012
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Change of Name
Mar 13, 2014
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Change of Address
Sep 3, 2014
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Release of U.S. Patent Agreement (for Non-U.S. Grantors)
Oct 12, 2018
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To: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
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Oct 30, 2020
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Release of Security Interest
Nov 2, 2020
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Release of Security Interest
Nov 2, 2020
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Change of Name
Sep 9, 2021
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To: MOSAID TECHNOLOGIES INCORPORATED
Reel/Frame 057449/0393 →
Change of Name
Sep 9, 2021
From: CONVERSANT INTELLECTUAL PROPERTY INC.
To: MOSAID TECHNOLOGIES INCORPORATED
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Corrective Assignment to Correct the Conveying Party's Name Previously Recorded at Reel: 057449 Frame: 0393. Assignor(S) Hereby Confirms the Change of Name.
Aug 30, 2023
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Corrective Assignment to Correct the Conveying Party's Name Previously Recorded at Reel: 057449 Frame: 0162. Assignor(S) Hereby Confirms the Change of Name.
Aug 30, 2023
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