Memory device and method for repairing a semiconductor memory
View Patent ↗A block repair device is used in a Dynamic Random Access Memory (DRAM) having a primary array with a defective cell and a redundant array with a redundant row. The block repair device stores a block repair configuration that determines the dimensions (e.g., the number of rows and columns spanned) of a repair block. Routing circuitry is configured by the stored block repair configuration to output some row and column address bits from received row and column addresses in a selected ratio. Comparison circuitry compares the row and column address bits output by the routing circuitry with the address of the defective cell that defines the repair block. When a match occurs, the comparison circuitry implements a block repair by activating the redundant row and by causing data to be written to or read from the activated redundant row instead of the primary array.
1. A memory device comprising:
a memory array having a plurality of rows and columns;
a redundant row;
a first set of nonvolatile elements for storing a plurality of address bits identifying a region of the memory array containing a defective bit; and
a second set of nonvolatile elements for storing one of a plurality of possible block repair configurations, and
wherein at least one element of the first set of nonvolatile elements:
stores a row address bit when configured in accordance with a first block repair configuration; and
stores a column address bit when configured in accordance with a second block repair configuration.
2. The memory device as claimed in claim 1 wherein each of the first set of nonvolatile elements is configured to store one of a row address bit and a column address bit.
3. The memory device as claimed in claim 2 wherein the first block repair configuration indicates replacing an entire row in the memory array with the redundant row.
4. The memory device as claimed in claim 2 wherein the second block repair configuration indicates replacing an entire column in the memory array with the redundant row.
5. The memory device as claimed in claim 1 wherein the second set of nonvolatile elements comprises a plurality of nonvolatile elements for storing more than two block repair configurations.
6. The memory device as claimed in claim 1 wherein the first block repair configuration indicates a first number of bits to repair, the second block repair configuration indicating a second number of bits to repair, the first number and the second number being equal.
7. The memory device as claimed in claim 1 wherein the one of the block repair configurations indicates one of a block repair and a row repair.
8. The memory device as claimed in claim 7 wherein the one of the block repair configurations defines dimensions of a repair block.
9. The memory device as claimed in claim 1 wherein the nonvolatile elements are selected from a group comprising fuses, anti-fuses, and Flash EEPROM cells.
10. The memory device as claimed in claim 1 wherein the number of the plurality of rows is a power of two number.
11. The memory device as claimed in claim 1 wherein the number of the plurality of columns is a power of two number.
12. The memory device as claimed in claim 1 wherein the redundant row is one of a plurality of redundant rows in a redundant array of the memory device.
13. A method of operating a Dynamic Random Access Memory (DRAM) comprising:
receiving a row address;
activating a primary row in a main memory array corresponding to a row address;
comparing a first subset of bits of the row address to a first selection of bits from a first set of nonvolatile elements storing a plurality of address bits, the first subset of bits and the first selection of bits defined by a second set of nonvolatile elements storing a block repair configuration;
activating a redundant row in response to the first subset of bits matching the first selection of bits;
receiving a column address;
comparing a second subset of bits of the column address to a second selection of bits from the first set of nonvolatile elements other than the first selection of bits, the second subset of bits and the second selection of bits defined by the second set of nonvolatile elements; and
accessing the redundant row in response to the second subset of bits matching the second selection of bits, and accessing the primary row in response to the second subset of bits failing to match the second selection of bits.
14. The method as claimed in claim 13 wherein the redundant row is one of a plurality of redundant rows in a redundant array of the DRAM.
15. The method as claimed in claim 13 wherein the nonvolatile elements are selected from a group comprising fuses, anti-fuses, and Flash EEPROM cells.
16. The method as claimed in claim 13 wherein the primary row is one of a number of primary rows in the main memory array, the number of primary rows being a power of two number.