Memory cell arrays
View Patent ↗A memory device includes memory cells, bit lines, active area lines running generally in parallel to the bit lines, and transistors formed in each active area line and electrically coupling memory cells to corresponding bit lines. Each bit line includes slanted portions that intersect a corresponding portion of an active area line at an angle. Contacts electrically coupling the bit line to portions of the active area line are formed in a region generally defined by the angled intersection of the bit line to the active area line. The memory cells can have an area of about 6F 2 , and the bit lines can be coupled to sense amplifiers in a folded bit line configuration. Each bit line includes a first level portion and a second level portion.
1. A semiconductor device, comprising:
memory cells each having an area of about 6F 2 ;
sense amplifiers;
bit lines coupled to the sense amplifiers in a folded bit line configuration, each bit line including a first level portion and a second level portion; and
active area lines, transistors being formed in the active area lines and electrically coupling corresponding memory cells to corresponding first level bit lines.
2. The semiconductor device of claim 1 , wherein each pair of bit lines is vertically twisted at one or more predetermined locations, the bit lines in the pair transitioning between the first level portion and the second level portion at each twist.
3. The semiconductor device of claim 2 , wherein a column pitch of each memory cell is 2F.
4. The semiconductor device of claim 1 , wherein each memory cell includes a capacitor formed over the first level portion of each bit line.
5. The semiconductor device of claim 4 , wherein the second level portion of each bit line is formed over each capacitor.
6. The semiconductor device of claim 1 , wherein the bit lines extend generally along the same direction as the active area lines, the bit lines intersecting the active area lines at slanted portions,
the semiconductor device further comprising contacts between the bit lines and active area lines formed in the slanted portions.
7. The semiconductor device of claim 6 , wherein the active area lines are generally straight and the bit lines extend in a wavy pattern.
8. The semiconductor device of claim 6 , wherein the bit lines are generally straight and the active area lines extend in a wavy pattern.
9. The semiconductor device of claim 6 , wherein the bit lines extend along generally the same direction as the active area lines so that the bit lines and active area lines intersect at predetermined locations.
10. The semiconductor device of claim 1 , wherein in the folded bit line arrangement a pair of bit lines is coupled to a same side of each corresponding sense amplifier.
11. A semiconductor device, comprising:
memory cells each having an area of about 6F 2 :
sense amplifiers;
bit lines coupled to the sense amplifiers in a folded bit line configuration, each bit line including a first level portion and a second level portion; and
active area lines, transistors being formed in the active area lines and electrically coupling corresponding memory cells to corresponding first level bit lines,
wherein the bit lines extend generally along the same direction as the active area lines, the bit lines intersecting the active area lines at slanted portions,
the semiconductor device further comprising contacts between the bit lines and active area lines formed in the slanted portions,
each bit line having a first portion on a first side of a corresponding active area line, a second portion on a second side of the corresponding active area line, and a third portion on the first side of the active area line.
12. A memory device comprising:
memory cells each having an area of about 6F 2 ;
sense amplifiers;
bit lines coupled to the sense amplifiers in a folded bit line arrangement;
active area lines; and
transistors formed in the active area lines and electrically coupling corresponding memory cells to corresponding bit lines.
13. The memory device of claim 12 , wherein each bit line has a first level portion and a second level portion, each transistor electrically coupling a corresponding memory cell to a first level portion of a corresponding bit line.
14. The memory device of claim 13 , wherein each pair of bit lines is vertically twisted at one or more predetermined locations, the bit lines in the pair transitioning between the first level portion and the second level portion at each twist.
15. The memory device of claim 13 , wherein each memory cell includes a capacitor formed over the first level portion of each bit line.
16. The memory device of claim 15 , wherein the second level portion of each bit line is formed over each capacitor.
17. The memory device of claim 12 , wherein the bit lines extend generally along the same direction as the active area lines, the bit lines intersecting the active area lines at slanted portions.
18. The memory device of claim 12 , wherein each pair of bit lines is coupled to one side of a corresponding sense amplifier.
19. The memory device of claim 12 , wherein in the folded bit line arrangement a pair of bit lines is coupled to a same side of each corresponding sense amplifier.
20. A method of making a memory device, comprising:
forming memory cells each having an area of about 6F 2 ;
forming sense amplifiers;
coupling bit lines to the sense amplifiers in a folded bit line arrangement;
forming transistors in active area lines; and
the transistors electrically coupling corresponding memory cells to corresponding bit lines.
21. The method of claim 20 , wherein coupling the bit lines to the sense amplifiers in the folded bit line arrangement comprises coupling each pair of bit lines to a same side of each corresponding sense amplifier.
22. A method of making a memory device, comprising:
forming memory cells each having an area of about 6F 2 ;
forming sense amplifiers;
coupling bit lines to the sense amplifiers in a folded bit line arrangement;
forming transistors in active area lines;
the transistors electrically coupling corresponding memory cells to corresponding bit lines;
forming each bit line of a first level portion and a second level portion; and
coupling each transistor to the first level portion of the corresponding bit line.
23. The method of claim 22 , further comprising:
vertically twisting each pair of bit lines at one or more predetermined locations; and
transitioning the bit lines in the pair between the first level portion and the second level portion at each twist.
24. The method of claim 23 , further comprising forming a capacitor of each memory cell over the first level portion of each bit line.
25. The method of claim 24 , further comprising forming the second level portion of each bit line over the capacitor.