Synchronous DRAM with selectable internal prefetch size
View Patent ↗A synchronous memory device and its method of operation which can be set to operate at a plurality of supported prefetch modes. The prefetch mode may be set by programming a portion of a mode register of the memory device or by setting one or more programmable elements. For read operations, the synchronous memory device internally reads data corresponding to the largest supported prefetch size, and outputs read data corresponding to the current mode. For write operations the synchronous memory accepts write data corresponding to the selected prefetch mode and writes the received data to the array. Data words corresponding to data not received are masked from writing via a write masking circuit.
1. A method of operating a memory device supporting a data transfer operation in a plurality of prefetch modes, said method comprising the steps of:
detecting a current prefetch mode from a reprogrammable element of said memory device;
if the current prefetch mode corresponds to a first prefetch mode, transferring without masking, a first plurality of words between said memory device and an external device at a rate of one word per data transfer period; and
if the current prefetch mode corresponds to a second prefetch mode, transferring while masking a second plurality of words between said memory device and an external device at a rate of one word per data transfer period;
wherein said second plurality is less than said first plurality.
2. The method of claim 1 , further comprising:
reprogramming said reprogrammable element to store an updated current prefetch mode; and
re-detecting the current prefetch mode by reading the updated current prefetch mode stored in said reprogrammable element.
3. The method of claim 2 , wherein said data transfer operation is a read and said masking further comprises not outputting to the external device a portion of a read latch.
4. The method of claim 2 , wherein said data transfer operation is a write and said masking further comprises not writing to at least one memory array of said memory device a portion of at least one input register of said memory device.
5. The method of claim 2 , wherein said first plurality is four.
6. The method of claim 2 , wherein said second plurality is two.
7. The method of claim 2 , wherein said reprogrammable element is at least a portion of a mode register of said memory device.
8. The method of claim 2 , wherein said reprogrammable element comprises at least one pin of said memory device.
9. The method of claim 2 , wherein said data transfer period is one clock cycle.
10. The method of claim 2 , wherein said data transfer period is one half clock cycle.
11. A method of operating a memory device supporting a data transfer operation in a plurality of prefetch modes, said method comprising the steps of:
selecting a first one of the plurality of prefetch modes for storage in a portion of said memory device;
detecting a current prefetch mode by determining a stored content of said portion of said memory device;
if the current prefetch mode corresponds to a first prefetch mode, transferring without masking, a first plurality of words between said memory device and an external device at a rate of one word per data transfer period; and
if the current prefetch mode corresponds to a second prefetch mode, transferring while masking a second plurality of words between said memory device and an external device at a rate of one word per data transfer period;
wherein said second plurality is less than said first plurality.
12. The method of claim 11 , further comprising:
selecting a second one of the plurality of prefetch modes;
storing the second one of the plurality of prefetch modes in said portion of said memory device; and
re-detecting the current prefetch mode by determining the stored content of said portion of said memory device.
13. The method of claim 12 , wherein said data transfer operation is a read and said masking further comprises not outputting to the external device a portion of a read latch.
14. The method of claim 12 , wherein said data transfer operation is a write and said masking further comprises not writing to at least one memory array of said memory device a portion of at least one input register of said memory device.
15. The method of claim 12 , wherein said first plurality is four.
16. The method of claim 12 , wherein said second plurality is two.
17. The method of claim 12 , wherein said portion of said memory device is at least a portion of a mode register of said memory device.
18. The method of claim 12 , wherein said data transfer period is one clock cycle.
19. The method of claim 12 , wherein said data transfer period is one half clock cycle.
20. A memory device comprising:
a memory array;
a data transfer circuit for performing a read operation by transferring a plurality of words from the memory array to an external device and for performing a write operation by transferring at least some of said plurality of words from the external device to the memory array; and
a reprogrammable element for storing one of a plurality of prefetch modes;
wherein said data transfer circuit transfers data between the memory device and an external device at a rate of one word per data transfer period, and operates in accordance with the prefetch mode stored in said reprogrammable element, the plurality of prefetch modes including, at least, a first prefetch mode to transfer a first number of words without masking, and a second prefetch mode to transfer a second number of words by masking at least one of said first number of words, said second number being less than said first number.
21. The memory device of claim 20 , wherein said reprogrammable element is located in a mode register of said memory device.
22. The memory device of claim 20 , wherein said reprogrammable element comprises at least one pin of said memory device.
23. The memory device of claim 20 , wherein the data transfer circuit, during a read operation in said second prefetch mode, masks said at least one of said first number of words by only transferring to the external device said second number of words.
24. The memory device of claim 20 , wherein the data transfer circuit, during a write operation in said second prefetch mode, masks said at least one of said first number of words by only transferring said second number of words to the memory array.
25. The memory device of claim 24 , wherein said portion of the memory array corresponding to the portion of the first number of words not included in said second number of words is write protected.
26. The memory device of claim 20 , wherein the data transfer period is one clock cycle.
27. The memory device of claim 20 , wherein the data transfer period is one half of a clock cycle.
28. A system comprising:
a processor; and
a memory coupled to said processor, wherein said memory further comprises:
a memory array,
a data transfer circuit for performing a read operation by transferring a plurality of words from the memory array to an external device and for performing a write operation by transferring at least some of said plurality of words from the external device to the memory array, and
a reprogrammable element for storing one of a plurality of prefetch modes;
wherein said data transfer circuit transfers data between the memory device and an external device at a rate of one word per data transfer period, and operates in accordance with the prefetch mode stored in said reprogrammable element, the plurality of prefetch modes including, at least, a first prefetch mode to transfer a first number of words without masking, and a second prefetch mode to transfer a second number of words by masking at least one of said first number of words, said second number being less than said first number.
29. The system of claim 28 , wherein said reprogrammable element is located in a mode register of said memory device.
30. The system of claim 28 , wherein said reprogrammable element comprises at least one pin of said memory.
31. The system of claim 28 , wherein the data transfer circuit, during a read operation in said second prefetch mode, masks said at least one of said first number of words by only transferring to the external device said second number or words.
32. The system of claim 28 , wherein the data transfer circuit, during a write operation in said second prefetch mode, masks said at least one of said first number of words by only transferring said second number of words to the memory array.
33. The system of claim 32 , wherein said portion of the memory array corresponding to the portion of the first number of words not included in said second number of words is write protected.
34. The system of claim 28 , wherein the data transfer period is one clock cycle.
35. The system of claim 28 , wherein the data transfer period is one half of a clock cycle.