Patent Assignment
Reel/Frame 054372/0194
Release of Security Interest
Recorded: 2020-11-10
Pages: 75
Assignor
CPPIB CREDIT INVESTMENTS INC.
Executed: 2020-10-28
Assignee
CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
515 LEGGET DRIVE, SUITE 704, OTTAWA, K2K 3G4, CANADA
Covered Properties
(68)
Transistor Having Enhanced Metal Silicide and a Self-Aligned Gate Electrode
Patent:
6,410,967 →
Application:
09/173,273 →
Method and Test Structure for Low-Temperature Integration of High Dielectric Constant Gate Dielectrics into Self-Aligned Semiconductor Devices
Patent:
6,210,999 →
Application:
09/205,047 →
Sacrificial Tin Arc Layer for Increased Pad Etch Throughput
Patent:
7,071,101 →
Application:
09/208,325 →
Dual Damascene Arrangement for Metal Interconnection with Oxide Dielectric Layer and Low K Dielectric Constant Layer
Patent:
6,380,091 →
Application:
09/238,050 →
Aluminum Disposable Spacer to Reduce Mask Count in Cmos Transistor Formation
Patent:
6,265,253 →
Application:
09/305,098 →
Phosphoric Acid Process for Removal of Contact Barc Layer
Patent:
6,127,259 →
Application:
09/372,443 →
Method of fabricating a deep source/drain
Patent:
6,358,803 →
Application:
09/489,369 →
Delay Locking High Speed Clock Synchronization Method And Circuit
Patent:
6,310,822 →
Application:
09/498,739 →
Semiconductor memory having segmented row repair
Patent:
6,314,030 →
Application:
09/594,442 →
Nickel Silicide Process Using Non-Reactive Spacer
Patent:
6,724,051 →
Application:
09/679,877 →
Slotted Trench Dual Inlaid Structure and Method of Forming Thereof
Patent:
6,524,947 →
Application:
09/774,800 →
Recessed Source Drains to Reduce Fringing Capacitance
Patent:
6,531,347 →
Application:
09/776,713 →
Fabrication of P-Channel Field Effect Transistor with Minimized Degradation of Metal Oxide Gate
Patent:
6,365,450 →
Application:
09/809,706 →
Method of Forming Semiconductor Devices with Differently Composed Metal-Based Gate Electrodes
Patent:
6,518,154 →
Application:
09/813,310 →
Semiconductor Device with Variable Composition Low-K Inter-Layer Dielectric and Method of Making
Patent:
6,518,646 →
Application:
09/819,615 →
Method of Fabricating a Semiconductor Device Having a Mos Transistor with a High Dielectric Constant Material
Patent:
6,686,248 →
Application:
09/825,658 →
Method of Strengthening Photoresist to Prevent Pattern Collapse
Patent:
6,635,409 →
Application:
09/902,568 →
Gradated Barrier Layer in Integrated Circuit Interconnects
Patent:
6,462,416 →
Application:
09/905,469 →
Semiconductor Memory Having Segmented Row Repair
Anneal Hillock Suppression Method in Integrated Circuit Interconnects
Patent:
6,500,754 →
Application:
09/999,661 →
Method for Lateral Trimming of Spacers
Patent:
6,821,713 →
Application:
10/085,242 →
Erase Block Architecture for Non-Volatile Memory
Patent:
6,587,383 →
Application:
10/100,856 →
Synchronous Dram with Selectable Internal Prefetch Size
Circuit, System and Method for Selectively Turning Off Internal Clock Drivers
Contiguous Block Addressing Scheme
Methods for Improving Carrier Mobility of Pmos and Nmos Devices
Patent:
6,573,172 →
Application:
10/244,439 →
Double Gate Semiconductor Device Having Separate Gates
Patent:
6,611,029 →
Application:
10/290,158 →
Method of Controlling the Chemical Mechanical Polishing of Stacked Layers Having a Surface Topology
Method of Manufacturing Semiconductor Devices
Method for Repairing a Semiconductor Memory
Erase Block Architecture for Non-Volatile Memory
Method of Manufacturing Semiconductor Device Comprising Silicon-Rich Tasin Metal Gate Electrode
Patent:
6,861,350 →
Application:
10/464,508 →
Narrow Fins by Oxidation in Double-Gate Finfet
Patent:
6,812,119 →
Application:
10/614,052 →
Narrow Body Raised Source/Drain Metal Gate Mosfet
Patent:
7,034,361 →
Application:
10/653,234 →
Slurry-Less Polishing for Removal of Excess Interconnect Material During Fabrication of a Silicon Integrated Circuit
Patent:
7,141,502 →
Application:
10/673,597 →
Demonstration Control Adjunct Device for Printers
Technique for Forming Recessed Sidewall Spacers for a Polysilicon Line
Internal Power Management Scheme for a Memory Chip in Deep Power Down Mode
End-Of-Range Defect Minimization in Semiconductor Device
Patent:
7,091,097 →
Application:
10/933,424 →
Synchronous Dram with Selectable Internal Prefetch Size
Contiguous Block Addressing Scheme
Contiguous Block Addressing Scheme
Contiguous Block Addressing Scheme
Synchronous Dram with Selectable Internal Prefetch Size
Internal Power Management Scheme for a Memory Chip in Deep Power Down Mode
Providing Stress Uniformity in a Semiconductor Device
Circuit, System and Method for Selectively Turning Off Internal Clock Drivers
Soi Semiconductor Components and Methods for Their Fabrication
Technique for Providing Stress Sources in Transistors in Close Proximity to a Channel Region by Recessing Drain and Source Regions
Non-Volatile Memory Devices and Control and Operation Thereof
Methods for Fabricating an Integrated Circuit
Conductor Bump Method and Apparatus
Reducing Transistor Junction Capacitance by Recessing Drain and Source Regions
Method of Forming a Semiconductor Structure Comprising an Implantation of Ions of a Non-Doping Element
Memory Device and Method for Repairing a Semiconductor Memory
Non-Volatile Memory Devices and Control and Operation Thereof
Soi Semiconductor Components and Methods for Their Fabrication
Contacts and Vias of a Semiconductor Device Formed by a Hard Mask and Double Exposure
Circuit, System and Method for Selectively Turning Off Internal Clock Drivers
Technique for Providing Stress Sources in Transistors in Close Proximity to a Channel Region by Recessing Drain and Source Regions
Reducing Transistor Junction Capacitance by Recessing Drain and Source Regions
Conductor Bump Method and Apparatus
Non-Volatile Memory Devices and Control and Operation Thereof
Non-Volatile Memory Devices and Control and Operation Thereof
Circuit, System and Method for Selectively Turning Off Internal Clock Drivers
Synthetic Barcode Payment System and Method
Patent:
9,239,979 →
Application:
14/598,219 →
Circuit, System and Method for Selectively Turning Off Internal Clock Drivers
Hybrid Wireless Short Range Payment System and Method
Related Assignments
(14)
Other recorded transfers of the patents in this record — the chain of ownership.
U.S. Intellectual Property Security Agreement (for Non-U.S. Grantors) - Short Form
Jan 10, 2012
From: 658276 N.B. LTD.; 658868 N.B. INC.; MOSAID TECHNOLOGIES INCORPORATED
To: ROYAL BANK OF CANADA
Reel/Frame 027512/0196 →
Change of Name
Mar 13, 2014
From: MOSAID TECHNOLOGIES INCORPORATED
To: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
Reel/Frame 032439/0638 →
Release of Security Interest
Aug 7, 2014
From: ROYAL BANK OF CANADA
To: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.; CONVERSANT IP N.B. 868 INC.; CONVERSANT IP N.B. 276 INC.
Reel/Frame 033484/0344 →
Change of Address
Sep 3, 2014
From: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
To: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
Reel/Frame 033678/0096 →
U.S. Patent Security Agreement (for Non-U.S. Grantors)
Sep 9, 2014
From: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
To: CPPIB CREDIT INVESTMENTS INC., AS LENDER; ROYAL BANK OF CANADA, AS LENDER
Reel/Frame 033706/0367 →
Assignment of Assignor's Interest
Feb 22, 2016
From: ADVANCED MICRO DEVICES, INC.
To: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
Reel/Frame 037876/0790 →
Amended and Restated U.S. Patent Security Agreement (for Non-U.S. Grantors)
Aug 22, 2018
From: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
To: CPPIB CREDIT INVESTMENTS, INC.
Reel/Frame 046900/0136 →
Release of U.S. Patent Agreement (for Non-U.S. Grantors)
Oct 12, 2018
From: ROYAL BANK OF CANADA, AS LENDER
To: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
Reel/Frame 047645/0424 →
Change of Name
Sep 9, 2021
From: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
To: MOSAID TECHNOLOGIES INCORPORATED
Reel/Frame 057709/0853 →
Change of Name
Sep 9, 2021
From: CONVERSANT INTELLECTUAL PROPERTY INC.
To: MOSAID TECHNOLOGIES INCORPORATED
Reel/Frame 057448/0207 →
Change of Name
Nov 3, 2021
From: CONVERSANT INTELLECTUAL PROPERTY INC.
To: MOSAID TECHNOLOGIES INCORPORATED
Reel/Frame 058796/0572 →
Change of Name
Nov 3, 2021
From: CONVERSANT INTELLECTUAL PROPERTY INC.
To: MOSAID TECHNOLOGIES INCORPORATED
Reel/Frame 058793/0720 →
Corrective Assignment to Correct the Conveying Party's Name Previously Recorded at Reel: 058796 Frame: 0572. Assignor(S) Hereby Confirms the Change of Name.
Aug 16, 2023
From: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
To: MOSAID TECHNOLOGIES INCORPORATED
Reel/Frame 064608/0757 →
Corrective Assignment to Correct the Conveying Party's Name Previously Recorded at Reel: 057448 Frame: 0207. Assignor(S) Hereby Confirms the Change of Name.
Aug 30, 2023
From: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
To: MOSAID TECHNOLOGIES INCORPORATED
Reel/Frame 064783/0033 →