Narrow body raised source/drain metal gate MOSFET
View Patent ↗A semiconductor device includes a fin, a source region formed adjacent the fin and having a height greater than that of the fin, and a drain region formed adjacent the a second side of the fin and having a height greater than that of the fin. A metal gate region is formed at a top surface and at least one side surface of the fin. A width of the source and drain region may be greater than that of the fin. The semiconductor device may exhibit a reduced series resistance and an improved transistor drive current.
1. A semiconductor FinFET device comprising:
an insulator;
a semiconductor layer formed on the insulator, the semiconductor layer including a fin portion corresponding to a channel of the semiconductor device;
a source region formed at a first end of the semiconductor layer, a height of the source region being higher than that of the fin;
a drain region formed at a second end of the semiconductor layer, a height of the drain region being higher than that of the fin;
a metal gate region formed to overlap at a top surface and at least one side surface of the fin; and
oxide sidewalls formed adjacent to the metal gate region and above the top surface of the fin.
2. The device of claim 1 , wherein the metal gate region overlaps the top surface and two side surfaces of the fin.
3. The device of claim 1 , wherein the source and drain regions are silicided.
4. The device of claim 1 , wherein a distance between the insulator and the metal gate region is about 500 Å to about 700 Å and a distance between the insulator and a top of the source or the drain region is about 600 Å to about 1000 Å.
5. The device of claim 1 , wherein the metal gate comprises at least one of tungsten, titanium, nickel, TaSiN, and TaN.
6. The semiconductor device of claim 1 , wherein the sidewall spacers have a width ranging from about 150 Å to about 1000 Å.
7. A FinFET device comprising:
an insulator;
a semiconductor layer formed on the insulator, the semiconductor layer including a fin portion corresponding to a channel of the semiconductor device;
a source region formed from a first end of the semiconductor layer, a height of the source region being higher than that of the fin and a width of the source region being wider than that of the fin;
a drain region formed from a second end of the semiconductor layer, a height of the drain region being higher than that of the fin and a width of the drain region being wider than that of the fin;
a metal gate region formed to overlap at a top surface and at least one side surface of the fin; and
sidewalls spacers formed adjacent at least portions of the metal gate region.
8. The FinFET device of claim 7 , wherein the sidewall spacers have a width ranging from about 150 Å to about 1000 Å.
9. The FinFET of claim 8 , wherein the source and drain regions are silicided.
10. The FinFET of claim 7 , wherein a thickness of the fin portion ranges from about 500 Å to about 700 Å and a thickness of the source and drain regions ranges from about 600 Å to about 1000 Å.