Patent Assignment
Reel/Frame 037876/0790
Assignment of Assignor's Interest
Recorded: 2016-02-22
Received: 2016-02-22
Pages: 12
Assignor
ADVANCED MICRO DEVICES, INC.
Executed: 2016-02-12
Assignee
CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
515 LEGGET DRIVE, SUITE 704, OTTAWA, ONC, K2K3G4, CANADA
Covered Properties
(30)
Reducing Transistor Junction Capacitance by Recessing Drain and Source Regions
Application:
12/791,290 →
Technique for Providing Stress Sources in Transistors in Close Proximity to a Channel Region by Recessing Drain and Source Regions
Application:
12/710,744 →
Contacts and Vias of a Semiconductor Device Formed by a Hard Mask and Double Exposure
Application:
12/537,321 →
Soi Semiconductor Components and Methods for Their Fabrication
Application:
12/413,185 →
Method of Forming a Semiconductor Structure Comprising an Implantation of Ions of a Non-Doping Element
Application:
12/037,533 →
Reducing Transistor Junction Capacitance by Recessing Drain and Source Regions
Application:
12/027,583 →
Conductor Bump Method and Apparatus
Application:
11/832,486 →
Methods for Fabricating an Integrated Circuit
Application:
11/689,764 →
Technique for Providing Stress Sources in Transistors in Close Proximity to a Channel Region by Recessing Drain and Source Regions
Application:
11/558,006 →
Soi Semiconductor Components and Methods for Their Fabrication
Application:
11/538,001 →
Providing Stress Uniformity in a Semiconductor Device
Application:
11/428,022 →
End-Of-Range Defect Minimization in Semiconductor Device
Application:
10/933,424 →
Technique for Forming Recessed Sidewall Spacers for a Polysilicon Line
Application:
10/786,401 →
Slurry-Less Polishing for Removal of Excess Interconnect Material During Fabrication of a Silicon Integrated Circuit
Application:
10/673,597 →
Narrow Body Raised Source/Drain Metal Gate Mosfet
Application:
10/653,234 →
Narrow Fins by Oxidation in Double-Gate Finfet
Application:
10/614,052 →
Method of Manufacturing Semiconductor Device Comprising Silicon-Rich Tasin Metal Gate Electrode
Application:
10/464,508 →
Method of Controlling the Chemical Mechanical Polishing of Stacked Layers Having a Surface Topology
Application:
10/304,573 →
Double Gate Semiconductor Device Having Separate Gates
Application:
10/290,158 →
Methods for Improving Carrier Mobility of Pmos and Nmos Devices
Application:
10/244,439 →
Method for Lateral Trimming of Spacers
Application:
10/085,242 →
Anneal Hillock Suppression Method in Integrated Circuit Interconnects
Application:
09/999,661 →
Gradated Barrier Layer in Integrated Circuit Interconnects
Application:
09/905,469 →
Method of Strengthening Photoresist to Prevent Pattern Collapse
Application:
09/902,568 →
Method of Fabricating a Semiconductor Device Having a Mos Transistor with a High Dielectric Constant Material
Application:
09/825,658 →
Semiconductor Device with Variable Composition Low-K Inter-Layer Dielectric and Method of Making
Application:
09/819,615 →
Method of Forming Semiconductor Devices with Differently Composed Metal-Based Gate Electrodes
Application:
09/813,310 →
Fabrication of P-Channel Field Effect Transistor with Minimized Degradation of Metal Oxide Gate
Application:
09/809,706 →
Recessed Source Drains to Reduce Fringing Capacitance
Application:
09/776,713 →
Slotted Trench Dual Inlaid Structure and Method of Forming Thereof
Application:
09/774,800 →