SOI semiconductor components and methods for their fabrication

1. A method for fabricating a semiconductor component including a semiconductor on insulator (SOI) substrate having a first semiconductor layer of first conductivity type, a layer of insulator on the first semiconductor layer, and a second semiconductor layer overlying the layer of insulator, the method comprising the steps of:

forming an insulating region extending through the second semiconductor layer to the layer of insulator;

implanting conductivity determining ions into the first semiconductor layer to form a drift region of second conductivity type;

etching a first opening exposing a portion of the drift region and a second opening exposing a portion of the first semiconductor layer adjacent the drift region;

forming a gate electrode overlying the first semiconductor layer adjacent the drift region;

implanting conductivity determining ions into the drift region to form a drain region and into the first semiconductor layer to form a source region, the drain region and source region of second conductivity type; and

forming an electrical contact to the gate electrode, the drain region, and the source region.

2. The method of claim 1 further comprising the step of forming a gate insulating layer overlying the portion of the first semiconductor layer adjacent the drift region.

3. The method of claim 2 wherein the step of forming a gate electrode comprises the steps of:

depositing a layer of polycrystalline silicon; and

patterning the polycrystalline silicon to form a gate electrode overlying the gate insulating layer.

4. The method of claim 3 wherein the step of patterning the polycrystalline silicon to form a gate electrode further comprises the step of patterning the polycrystalline silicon to form a gate electrode at least partially overlying the insulating region positioned over the drift region.

5. The method of claim 2 wherein the step of forming a gate electrode comprises the steps of:

depositing a layer of gate electrode forming material to fill the first opening and the second opening;

planarizing an upper surface of the layer of gate electrode forming material; and

patterning the layer of gate electrode forming material to form the gate electrode.

6. The method of claim 2 wherein the step of forming a gate electrode comprises the steps of:

depositing a layer of polycrystalline silicon overlying the gate insulator;

planarizing an upper surface of the layer of polycrystalline silicon;

after the step of planarizing,

forming a layer of gate insulator material overlying the second semiconductor layer,

depositing a layer of gate electrode forming material overlying the layer of gate insulator material, and

pattering the layer of gate electrode forming material to form a P-channel MOS transistor gate electrode and an N-channel MOS transistor gate electrode;

removing the layer of polycrystalline silicon; and

forming a metal gate electrode overlying the gate insulating layer adjacent the drift region.

7. The method of claim 1 wherein the step of forming a gate insulating layer comprises the step of:

forming a gate insulating layer in the portion of the first semiconductor layer along a boundary of the drift region.

8. The method of claim 7 wherein the step of forming a gate electrode comprises the step of:

forming a gate electrode contacting the gate insulating layer formed in the portion of the first semiconductor layer along the boundary of the drift region.

9. The method of claim 7 wherein the step of forming a gate electrode comprises the step of:

forming a gate electrode contacting the gate insulating layer formed in the portion of the first semiconductor layer along the boundary of the drift region, overlying a portion of the insulating region and overlying a portion of the drift region.

10. A method for fabricating a semiconductor component including a semiconductor on insulator (SOI) substrate having a first semiconductor layer of first conductivity type, a layer of insulator on the first semiconductor layer, and a second semiconductor layer overlying the layer of insulator, the method comprising the steps of:

forming first and second insulating regions extending through the second semiconductor layer to the layer of insulator, the first and second insulating regions separated by a portion of the second semiconductor layer;

forming a drift region of second conductivity type in the first semiconductor layer, the drift region positioned underlying first insulating region and the portion of the second semiconductor layer;

etching a first opening through the first insulating region to expose a portion of the drift region and a second opening through the second insulating region to expose a portion of the first semiconductor layer;

depositing a gate electrode forming material to fill the first opening and the second opening;

planarizing a surface of the gate electrode forming material;

patterning the gate electrode forming material to form a gate electrode overlying the first semiconductor layer adjacent the drift region;

forming a source region of second conductivity type in the first semiconductor layer and a drain region of second conductivity type in the drift region; and

forming an electrical contact to the source region, the drain region, and the gate electrode.

11. The method of claim 10 wherein the step of forming an electrical contact to the gate electrode further comprises the step of forming an electrical contact to the portion of the second semiconductor layer.

12. The method of claim 10 wherein the step of etching comprises the step of etching through the first insulating region and the second insulating region using the portion of the second semiconductor layer as an etch mask.

13. A method for fabricating a semiconductor component including a semiconductor on insulator (SOI) substrate having a first semiconductor layer of first conductivity type, a layer of insulator on the first semiconductor layer, and a second semiconductor layer overlying the layer of insulator, the method comprising the steps of:

impurity doping a first portion of the first semiconductor layer to form a drift region of second conductivity type;

forming a gate insulating layer overlying a second portion of the first semiconductor layer;

depositing a gate electrode material overlying the gate insulating layer;

impurity doping a portion of the drift region to form a drain region of second conductivity type and a third portion of the first semiconductor layer to form a source region of second conductivity type;

forming a P-channel MOS transistor in and on the second semiconductor layer; and

forming an N-channel MOS transistor in and on the second semiconductor layer.

14. The method of claim 13 further comprising the steps of:

forming an insulating region extending through the second semiconductor layer; and

etching first and second opening through the insulating region and the layer of insulator, the first opening overlying a portion of the drift region and the second opening overlying the second portion and the third portion of the first semiconductor layer.

15. The method of claim 14 wherein the step of etching comprises the step of etching the first opening and the second opening separated by a portion of the insulating region.

16. The method of claim 15 wherein the step of depositing a gate electrode material comprises the step of depositing a layer of polycrystalline silicon into the first opening and the second opening.

17. The method of claim 16 further comprising the step of patterning the layer of polycrystalline silicon to form a gate electrode overlying the gate insulating layer and the portion of the insulating region.

18. The method of claim 16 further comprising the steps of:

planarizing a surface of the layer of polycrystalline silicon; and

etching the layer of polycrystalline silicon to form a gate electrode overlying the gate insulating layer.

19. The method of claim 16 further comprising the step of planarizing a surface of the layer of polycrystalline silicon and wherein the steps of forming a P-channel MOS transistor and forming an N-channel MOS transistor follow the step of planarizing.

20. The method of claim 19 further comprising the steps of:

removing the layer of polycrystalline silicon; and

forming a metallic gate electrode overlying the gate insulating layer.