End-of-range defect minimization in semiconductor device

1. A method of fabricating a semiconductor device having reduced junction leakage, the method comprising the steps of:

A. forming a gate electrode over a substrate;

B. forming deep amorphous regions to a first depth by pre-amorphisization implantation;

C. implanting dopants within the deep amorphous regions to form amorphisized source/drain regions to a second depth, which is less than the first depth;

D. forming intermediate amorphous regions by partially recrystallizing portions of the deep amorphous regions to a third depth, which is less than the first depth, but at least as deep as the second depth; and

E. recrystallizing the intermediate amorphous regions and activating the dopants to form final source/drain regions to a depth about equal to the third depth such that deep amorphous regions are located beneath the final source/drain regions and the final source/drain regions comprise activated dopants throughout the final source/drain regions.

2. The method of claim 1 , wherein the recrystallizing of step E comprises high dose laser thermal annealing.

3. The method of claim 1 , wherein the partially recrystallizing of step D comprises using solid phase epitaxy.

4. The method of claim 3 , wherein the solid phase epitaxy is by low dose laser thermal annealing or by low temperature soak annealing.

5. The method of claim 1 , wherein the forming deep amorphous regions of step B comprises implanting neutral ions into the substrate.

6. The method of claim 1 , wherein the difference between the first depth and the third depth is at least about 150 angstroms.

7. The method of claim 1 , wherein step D is accomplished prior to step C.

8. A method of fabricating a semiconductor device having reduced junction leakage, the method comprising the step of:

A. forming a gate electrode over a substrate;

B. forming source/drain extensions in the substrate to a depth d;

C. forming spacers adjacent to the gate electrode that mask portions of the source/drain extensions proximate to the gate electrode;

D. forming amorphous regions to a depth D1 by pre-amorphisization implantation of exposed portions of the source/drain extensions, where D1>d;

E. implanting dopants within the amorphous regions to form amorphisized source/drain regions to a depth D2, where d<D2<D1;

F. forming intermediate amorphous regions by partially recrystallizing portions of the amorphous regions to a depth D3, where D2<D3<D1; and

G. recrystallizing the intermediate amorphous regions and activating the dopants to form final source/drain regions at a depth D, which is about equal to D3 such that deep amorphous regions are located beneath the final source/drain regions and the final source/drain regions comprise activated dopants throughout the final source/drain regions.

9. The method of claim 8 , wherein step B comprises:

B.1 forming amorphous source/drain extension regions to a depth d1 by pre-amorphisization implantation, where d1>d;

B.2 implanting dopants within the amorphous source/drain extension regions to form amorphisized source/drain regions to a depth d2, where d2<d1;

B.3 forming intermediate amorphous source/drain extension regions by partially recrystallizing portions of the amorphous source/drain extension regions to a depth d3, where d2≦d3<d1; and

B.4 recrystallizing the intermediate amorphous source/drain extension regions and activating the dopants to form final source/drain extension to the depth d, which is about equal to d3.

10. The method of claim 8 , wherein the difference between the D1 and D is at least about 150 angstroms.

11. The method of claim 8 , wherein the partially recrystallizing of step F comprises using solid phase epitaxy by low dose laser thermal annealing or by low temperature soak annealing.

12. The method of claim 8 , wherein the recrystallizing of step G comprises high dose later thermal annealing.

13. A method of fabricating a semiconductor device having reduced junction leakage, the method comprising the steps of:

A. forming a gate electrode over a substrate;

B. forming amorphous source/drain extension regions in the substrate to a depth d1 by pre-amorphisization implantation;

C. forming spacers adjacent to the gate electrode that mask portions of the amorphous source/drain extension regions proximate to the gate electrode;

D. forming amorphous regions to a depth D1 by pre-amorphisization implantation of exposed portions of the source/drain extensions, where D1>d1;

E. implanting dopants within the amorphous regions to form amorphisized source/drain regions to a depth D2, where d1<D2<D1;

F. forming intermediate amorphous regions by partially recrystallizing portions of the amorphous regions to a depth D3, where D2<D3<D1; and

G. recrystallizing the intermediate amorphous regions and source/drain extension regions and activating the dopants to form final source/drain regions at a depth d in the source/drain extension regions beneath the spacers and a depth D in the intermediate amorphous regions, where d is about equal to d1 and D is about equal to D3 such that deep amorphous regions are located beneath the final source/drain regions and the final source/drain regions comprise activated dopants throughout the final source/drain regions.

14. The method of claim 13 , wherein the difference between the D1 and D is at least about 150 angstroms.

15. The method of claim 13 , wherein the partially recrystallizing of step F comprises using solid phase epitaxy by low dose laser thermal annealing or by low temperature soak annealing.

16. The method of claim 13 , wherein the recrystallizing of step G comprises high dose laser thermal annealing.

17. A semiconductor device having reduced junction leakage formed by a process comprising the steps of:

A. forming a gate electrode disposed on a substrate;

B. forming deep amorphous regions to a first depth by pre-amorphisization implantation;

C. implanting dopants within the deep amorphous regions to form amorphisized source/drain regions to a second depth, which is less than the first depth;

D. forming intermediate amorphous regions by partially recrystallizing portions of the deep amorphous regions to a third depth, which is less than the first depth, but at least as deep as the second depth; and

E. recrystallizing the intermediate amorphous regions and activating the dopants to form final source/drain regions to a depth about equal to the third depth such that deep amorphous regions are located beneath the final source/drain regions and the final source/drain regions comprise activated dopants throughout the final source/drain regions.

18. A semiconductor device having reduced junction leakage formed by a process comprising the steps of:

A. forming a gate electrode over a substrate;

B. forming source/drain extension in the substrate to a depth d;

C. forming spacers adjacent to the gate electrode that mask portions of the source/drain extensions proximate to the gate electrode;

D. forming amorphous regions to a depth D1 by pre-amorphisization implantation of exposed portions of the source/drain extensions, where D1>d;

E. implanting dopants within the amorphous regions to form amorphisized source/drain regions to a depth D2, where d<D2<D1;

F. forming intermediate amorphous regions by partially recrystallizing portions of the amorphous regions to a depth D3, where D2≦D3<D1; and

G. recrystallizing the intermediate amorphous regions and activating the dopants to form final source/drain regions at a depth D, which is about equal to D3 such that deep amorphous regions are located beneath the final source/drain regions and the final source/drain regions comprise activated dopants throughout the final source/drain regions.

19. The device of claim 18 , wherein step B comprises:

B.1 forming amorphous source/drain extension regions to a depth d1 by pre-amorphisization implantation, where d1>d;

B.2 implanting dopants within the amorphous source/drain extension regions to form amorphisized source/drain regions to a depth d2, where d2<d1;

B.3 forming intermediate amorphous source/drain extension regions by partially recrystallizing portions of the amorphous source/drain extension region to a depth d3, where d2≦d3<d1; and

B.4 recrystallizing the intermediate amorphous source/drain extension regions and activating the dopants to form final source/drain extensions to the depth d, which is about equal to d3.

20. A semiconductor device having reduced junction leakage formed by a process comprising the step of:

A. forming a gate electrode over a substrate;

B. forming amorphous source/drain extension regions in the substrate to a depth d1 by pre-amorphous implantation;

C. forming spacers adjacent to the gate electrode that mask portions of the amorphous source/drain extensions regions proximate to the gate electrode;

D. forming amorphous regions to a depth D1 by pre-amorphisization implantation of exposed portions of the source/drain extensions, where D1>d1;

E. implanting dopants within the amorphous regions to form amorphisized source/drain regions to a depth D2, where d1<D2<D1;

F. forming intermediate amorphous regions by partially recrystallizing portions of the amorphous regions to a depth D3, where D2<D3<D1; and

G. recrystallizing the intermediate amorphous regions and source/drain extension regions and activating the dopants to form final source/drain regions at a depth d in the source/drain extension regions beneath the spacers and a depth D in the intermediate amorphous regions, where d is about equal to d1 and D is about equal to D3 such that deep amorphous regions are located beneath the final source/drain regions and the final source/drain regions comprise activated dopants throughout the final source/drain regions.

21. A semiconductor device having reduced junction leakage, the semiconductor device comprising:

A. a gate electrode disposed on a substrate;

B. source/drain extensions formed within the substrate to a depth d and substantially adjacent to the gate electrode;

C. spacers formed on the substrate and adjacent to the gate electrode and configured to mask portions of the source/drain extension regions proximate to the gate electrode;

D. deep amorphous regions formed in the substrate to a depth D1, where d<D1; and

E. final source/drain regions comprising the source/drain extensions beneath the spacers and intermediate source/drain regions formed within the substrate to a depth D, where d<D<D1, and further comprising activated dopants distributed throughout the final source/drain regions.

22. The device of claim 21 , wherein the difference between the D1 and D is about at least 150 angstroms.