Conductor bump method and apparatus
View Patent ↗Various semiconductor die conductor structures and methods of fabricating the same are provided. In one aspect, a method of manufacturing is provided that includes forming a conductor structure on a conductor pad of a semiconductor die. The conductor layer has a surface. A polymeric layer is formed on the surface of the conductor layer while a portion of the surface is left exposed. A solder structure is formed on the exposed portion of the surface and a portion of the polymeric layer.
1. A method of manufacturing, comprising:
forming a conductor structure on a conductor pad of a semiconductor die, the conductor structure having a surface;
forming a polymeric layer on the surface of the conductor structure while leaving portions of the surface exposed;
forming a solder structure on each of the exposed portions of the surface, wherein a portion of each of the solder structures is positioned on the polymeric layer; and wherein a passivation structure is positioned on the conductor pad, the conductor structure is positioned on the passivation structure and a portion of the conductor structure is in electrical contact with the conductor pad by way of an opening in the passivation structure.
2. The method of claim 1 , wherein the forming the polymeric layer comprises forming a polyimide layer.
3. The method of claim 1 , wherein the forming the solder structures comprises plating a solder material.
4. The method of claim 3 , wherein the plating the solder material comprises plating a lead-free solder.
5. The method of claim 1 , wherein the forming the solder structures comprises stencil forming a solder material.
6. The method of claim 1 , wherein the forming the solder structures comprises a thermal reflow.
7. The method of claim 1 , wherein the forming the conductor structure comprises depositing metal and etching the metal to remove unwanted portions thereof.
8. The method of claim 1 , wherein the solder structures comprise power or ground input/outputs.
9. A method of manufacturing, comprising:
forming an underbump metallization structure on a conductor pad of a semiconductor die, the underbump metallization structure having a surface;
forming a polymeric layer on the surface of the underbump metallization structure while leaving portions of the surface exposed; and
bonding a solder structure on each of the exposed portions of the surface wherein a portion of each of the solder structures is positioned on the polymeric layer; and wherein a passivation structure is positioned on the conductor pad, the underbump metallization structure is positioned on the passivation structure and a portion of the underbump metallization structure is in electrical contact with the conductor pad by way of an opening in the passivation structure.
10. A method of manufacturing, comprising:
forming a conductor structure on a conductor pad of a semiconductor die, the conductor structure having a surface;
forming a polymeric layer on the surface of the conductor layer while leaving portions of the surface exposed;
forming a solder structure on each of the exposed portions of the surface, wherein a portion of each of the solder structures is positioned on the polymeric layer; and
coupling the semiconductor die to a first substrate; and wherein a passivation structure is positioned on the conductor pad, the conductor structure is positioned on the passivation structure and a portion of the conductor structure is in electrical contact with the conductor pad by way of an opening in the passivation structure.
11. The method of claim 10 , wherein the coupling the semiconductor die comprises flip-chip mounting.
12. The method of claim 10 , comprising coupling the first substrate to a second substrate.
13. The method of claim 10 , wherein the forming the polymeric layer comprises forming a polyimide layer.
14. The method of claim 10 , wherein the forming the solder structures comprises plating a solder material.
15. The method of claim 14 , wherein the plating the solder material comprises plating a lead-free solder.
16. The method of claim 10 , wherein the forming the solder structure comprises stencil forming a solder material.
17. The method of claim 10 , wherein the solder structures comprise power or ground input/outputs.
18. The method of claim 9 , wherein the solder structures comprise power or ground input/outputs.