Circuit, system and method for selectively turning off internal clock drivers
View Patent ↗The present invention includes a circuit, system and method for selectively turning off internal clock drivers to reduce operating current. The present invention may be used to reduce power consumption by reducing operating current in a memory device. Operating current may be reduced by turning off internal clock drivers that deliver a clock signal during selected periods of time. According to an embodiment of clock control circuitry of the present invention, an internal clock is disabled if a no operation command is detected during periods of time when no read or write burst operation is taking place. Methods, memory devices and computer systems including the clock control circuitry and its functionality are also disclosed.
1. Clock control circuitry, comprising:
command detection circuitry configured to generate a gating signal based on a command signal input having first possible signal states, where the command signal input is concurrent with an absence of a read/write burst operation, the gating signal; i) indicating idle time in a memory device when the command signal input to the memory device has the first possible signal states at one time, and ii) indicating otherwise when the command signal input has remaining possible signal states; and
clock gating circuitry coupled to said command detection circuitry for receiving a system clock and for selectively gating said system clock in response to said gating signal.
2. The clock control circuitry according to claim 1 , wherein said command detection circuitry comprises a 2-input NOR gate for sensing a read/write burst command.
3. The clock control circuitry according to claim 1 , wherein said clock gating circuitry comprises a 3-input NOR gate for receiving the command signal input.
4. The clock control circuitry according to claim 1 , further comprising delay circuitry for delaying said system clock to compensate for delays in said command detection circuitry.
5. The clock control circuitry according to claim 1 , wherein said memory device comprises a dynamic random access memory (DRAM).
6. The clock control circuitry of claim 1 , wherein said command detection circuitry monitors at least one of a row-address strobe (RAS) signal, a column-address strobe (CAS) signal, and a write enable signal (WE) to determine said command signal input.
7. The clock control circuitry of claim 1 , wherein determining the absence of said read/write burst operation comprises monitoring register burst control and enable out signals.
8. The clock control circuitry according to claim 1 , wherein said command detection circuitry is further configured to detect a read/write burst operation.
9. A memory device, comprising:
a memory array; and
clock control circuitry in communication with said memory array and for receiving a system clock, said clock control circuitry comprising:
command detection circuitry configured to generate a gating signal based on a command signal input having first possible signal states, where the command signal input is concurrent with an absence of a read/write burst operation, the gating signal indicating idle time in a memory device when the command signal i) input to the memory device has the first possible signal states at one time, and ii) indicating otherwise when the command signal input has remaining possible signal states; and
clock gating circuitry coupled to said command detection circuitry for receiving said system clock and for selectively gating said system clock in response to said gating signal.
10. The memory device according to claim 9 , wherein said command detection circuitry comprises a 3-input NAND gate for receiving the command signal input.
11. The memory device according to claim 9 , wherein said command detection circuitry comprises a 2-input NOR gate for sensing a read/write burst command.
12. The memory device according to claim 9 , wherein said clock gating circuitry comprises a 3-input NOR gate.
13. The memory device according to claim 9 , further comprising delay circuitry for delaying said system clock to compensate for delays in said command detection circuitry.
14. The memory device according to claim 9 , wherein said memory device comprises a dynamic random access memory (DRAM).
15. The memory device according to claim 9 , wherein said command detection circuitry is further configured to detect a read/write burst operation.