Synchronous DRAM with selectable internal prefetch size
View Patent ↗A synchronous memory device and its method of operation which can be set to operate at a plurality of supported prefetch modes. The prefetch mode may be set by programming a portion of a mode register of the memory device or by setting one or more programmable elements. For read operations, the synchronous memory device internally reads data corresponding to the largest supported prefetch size, and outputs read data corresponding to the current mode. For write operations the synchronous memory accepts write data corresponding to the selected prefetch mode and writes the received data to the array. Data words corresponding to data not received are masked from writing via a write masking circuit.
1. A memory device supporting a plurality of possible prefetch modes, including at least a maximum prefetch mode and a minimum prefetch mode, comprising:
a memory array;
a read circuit comprising a read latch and coupled to the memory array for transferring a first plurality of words corresponding to said maximum prefetch mode from said memory array to said read latch, and for transferring a second plurality of words from said read latch to an external device, wherein said second plurality is a controllable parameter of said read circuit and is equal to or less than said first plurality;
a programmable element for storing a current prefetch mode chosen from a plurality of possible prefetch modes; and
a control circuit coupled to said read circuit;
wherein said control circuit, in response to a read command, detects the current prefetch mode stored in said programmable element, and operates said read circuit by setting said second plurality to correspond to the current prefetch mode.
2. The memory device of claim 1 , wherein said read circuit further comprises a multiplexer coupled to the control circuit, and said transferring of the second plurality of words is performed by the multiplexer coupling a different portion of said read latch to a driver circuit on each of a plurality of data transfer periods.
3. The memory device of claim 1 , wherein said programmable element is at least a portion of a mode register of said memory device.
4. The memory device of claim 1 , wherein said programmable element comprises at least one fuse or anti-fuse.
5. The memory device of claim 1 , wherein said programmable element comprises at least one pin of said memory device.
6. The memory device of claim 1 , wherein said maximum prefetch mode is an integer multiple of said minimum prefetch mode.
7. The memory device of claim 6 , wherein said minimum prefetch mode is two words.
8. The memory device of claim 6 , wherein said maximum prefetch mode is four words.
9. A memory device comprising:
a memory array;
a write circuit coupled to said memory array for receiving a plurality of words from an external device to be stored in the memory device, said write circuit comprising:
at least one input register;
a control circuit coupled to said write circuit; and
a programmable element for storing a prefetch mode chosen from a plurality of possible prefetch modes;
wherein said control circuit, in response to a write command, detects a current prefetch mode stored in said programmable element; and causes said write circuit to transfer a number of said plurality of words corresponding to the stored prefetch mode which are received from the external device to the at least one input register.
10. The memory device of claim 9 , wherein said control circuit, in response to a write command, causes said write circuit to write the transferred words from said at least one input register to said memory array.
11. The memory device of claim 10 , wherein said write circuit further comprises a masking logic coupled to the control circuit for masking words not being transferred from said at least one input register to said memory array.
12. The memory device of claim 9 , wherein said programmable element is at least a portion of a mode register of said memory device.
13. The memory device of claim 9 , wherein said programmable element comprises at least one fuse or anti-fuse.
14. The memory device of claim 9 , wherein said programmable element comprises at least one pin of said memory device.
15. The memory device of claim 9 , wherein said plurality of possible prefetch modes includes a minimum prefetch mode and a maximum prefetch mode, and said maximum prefetch mode is an integer multiple of said minimum prefetch mode.
16. The memory device of claim 15 , wherein said minimum prefetch mode corresponds to transferring two words.
17. A memory device comprising:
a memory array;
a data transfer circuit for performing a read operation by transferring a plurality of words from the memory array to an external device and for performing a write operation by transferring at least some of said plurality of words from the external device to the memory array;
wherein said data transfer circuit is operable in at least
a first prefetch mode to transfer a first number of words without masking and
a second prefetch mode to transfer a second number of words, by masking at least one of said first number of words,
said second number being less than said first number.
18. The memory device of claim 17 , further comprising:
a programmable element for storing a prefetch mode,
wherein said data transfer circuit operates in accordance with the prefetch mode stored in said programmable element.
19. The memory device of claim 17 , wherein the data transfer circuit, during a read operation in said second prefetch mode, masks said at least one of said first number of words by only transferring to the external device said second number of words.
20. The memory device of claim 17 , wherein the data transfer circuit, during a write operation in said second prefetch mode, masks said at least one of said first number of words by only transferring said second number of words to the memory array.
21. The memory device of 20 , wherein said portion of the memory array corresponding to the portion of the first number of words not included in said second number of words is write protected.
22. A method for reading a memory device supporting a plurality of prefetch modes, said method comprising the steps of:
transferring a first plurality of words corresponding to a largest of said plurality of prefetch modes from at least one memory array of said memory device to a read latch of said memory device;
detecting a current prefetch mode from a state of a programmable element of said memory device;
if the current prefetch mode corresponds to a first prefetch mode,
transferring the first plurality of words from said read latch to an external device; and
if the current prefetch mode corresponds to a second prefetch mode,
transferring only a second plurality of words from said read latch to an external device,
wherein said second plurality is less than said first plurality.
23. The method of claim 22 , wherein said transferring a second plurality of words further comprises causing a multiplexer to couple a different portion of the read latch to an output driver on each data transfer period.
24. A method for writing a memory device supporting a plurality of possible prefetch modes, said method comprising the steps of:
detecting a current prefetch mode from the state of a programmable element of said memory device;
transferring, a plurality of words corresponding to the current prefetch mode from an external device to at least one input register of said memory device;
if the current prefetch mode corresponds to a first prefetch mode,
transferring the plurality of words corresponding to the current prefetch mode from said at least one input register to at least one memory array of the memory device; and
if the current prefetch mode corresponds to a second prefetch mode,
transferring the plurality of words corresponding to the current prefetch mode from said at least one register to at least one memory array of the memory device, while masking a portion of said at least one register not corresponding to the second prefetch mode from being written to the at least one memory array of the memory device.
25. The method of claim 24 , wherein said plurality of possible prefetch modes includes a minimum prefetch mode which corresponds to transferring two words.
26. The method of claim 24 , wherein said maximum prefetch mode corresponds to transferring four words.
27. A method for operating a memory device supporting a data transfer operation in a plurality of prefetch modes, said method comprising the steps of:
detecting a current prefetch mode from a state of a programmable element of said memory device;
if the current prefetch mode corresponds to a first prefetch mode,
transferring without masking, a first plurality of words between said memory device and an external device; and
if the current prefetch mode corresponds to a second prefetch mode,
transferring while masking, a second plurality of words between said memory device and an external device;
wherein said second plurality is less than said first plurality.
28. The method of claim 27 wherein said data transfer operation is a read and said masking further comprises not outputting to the external device a portion of a read latch.
29. The method of claim 27 wherein said data transfer operation is a write and said masking further comprises not writing to at least one memory array of said memory device, a portion of at least one input register of said memory device.
30. A system comprising:
a processor;
a memory coupled to said processor, wherein said memory further comprises,
a memory array;
a read circuit comprising a read latch and coupled to the memory array for transferring a first plurality of words corresponding to said maximum prefetch mode from said memory array to said read latch, and for transferring a second plurality of words from said read latch to an external device,
wherein said second plurality is a controllable parameter of said read circuit and is equal to or less than said first plurality;
a programmable element for storing a current prefetch mode chosen from a plurality of possible prefetch modes; and
a control circuit coupled to said read circuit;
wherein said control circuit, in response to a read command, detects the current prefetch mode stored in said programmable element, and operates said read circuit by setting said second plurality to correspond to the current prefetch mode.
31. A system comprising:
a processor;
a memory coupled to said processor, wherein said memory further comprises,
a memory array;
a write circuit coupled to said memory array for receiving one word of data per data transfer period from an external device to be stored in the memory device, said write circuit further comprising,
at least one input register;
a control circuit coupled to said write circuit; and
a programmable element for storing a prefetch mode chosen from a plurality of possible prefetch modes;
wherein said control circuit, in response to a write command, detects a current prefetch mode stored in said programmable element, and causes said write circuit to transfer a number of said plurality of words corresponding to the stored prefetch mode which are received from the external device to the at least one input register.
32. A system comprising:
a processor;
a memory coupled to said processor, wherein said memory further comprises,
a memory array;
a data transfer circuit for performing a read operation by transferring a plurality of words from the memory array to an external device and for performing a write operation by transferring at least some of said plurality of words from the external device to the memory array;
wherein said data transfer circuit transfers data between the memory device and an external device, and is operable in at least a first prefetch mode to transfer a first number of words without masking and a second prefetch mode to transfer a second number of words, by masking at least one of said first number of words, said second number being less than said first number.