Non-volatile memory devices and control and operation thereof
View Patent ↗An improved non-volatile erase block memory device apparatus and method is described that incorporates an improved addressing scheme to provide for extended addressing allowing redundant erase blocks that are not utilized to repair general use erase blocks of the main memory array to be accessed and utilized as additional storage space by an end user. The additional storage space formed by the unused redundant erase blocks and the specified storage space of the main memory array is presented to the end user as a single contiguous address space. Additionally, the redundant erase blocks can be utilized to repair any damaged erase block in the memory array of the non-volatile erase block memory or Flash memory device regardless of bank placement.
1. A flash memory integrated circuit chip comprising:
a flash memory array; and
an interface including:
an address interface having address lines configured to be coupled to a source external to the integrated circuit chip, and the address interface configured to enable access to an address range of a specified plurality of erase blocks of the flash memory array of a specified size corresponding to the address range; and
an extended address interface having at least one address line configured to be coupled to the external source, and the extended address interface configured to enable access to an extended address range of a plurality of additional erase blocks of the flash memory array, and
the extended address range of the plurality of additional erase blocks and the address range of the specified plurality of erase blocks form one or more ranges of user accessible general use addresses, and the sum of the one or more ranges of user accessible general use addresses is larger than the specified size of the flash memory array.
2. The flash memory integrated circuit chip as claimed in claim 1 wherein the extended address interface is configured to block access to additional erase blocks of the flash memory integrated circuit chip that are utilized to repair damaged erase blocks of the flash memory array.
3. The flash memory integrated circuit chip as claimed in claim 1 wherein the address range of the plurality of erase blocks and the extended address range of the plurality of additional erase blocks forms a unified contiguous address range.
4. The flash memory integrated circuit chip as claimed in claim 1 wherein the interface of the flash memory integrated circuit chip is configured to repair erase blocks by redirecting an access to an erase block to a selected additional erase block and block access to the selected additional erase block through the extended address interface.
5. The flash memory integrated circuit chip as claimed in claim 4 wherein the address range of the plurality of erase blocks and the extended address range of the plurality of additional erase blocks forms a unified contiguous address range and the selected additional erase block utilized to repair a damaged erase block is selected from the end of the contiguous address range.
6. The flash memory integrated circuit chip as claimed in claim 1 wherein the plurality of erase blocks of the flash memory array is a power-of-two number of erase blocks.
7. The flash memory integrated circuit chip as claimed in claim 1 further comprising control registers for volatile memory.
8. The flash memory integrated circuit chip as claimed in claim 7 wherein the control registers for volatile memory are RAM control registers.
9. A system comprising:
the flash memory integrated circuit chip as claimed in claim 1 ; and
the external source coupled to the flash memory integrated circuit chip.
10. The system as claimed in claim 9 wherein the external source is a processor.