IP Library Granted Patent US 6,892,318
Granted Patent B2
US 6,892,318 · App. 10/375,994 · Granted May 10, 2005

Method for repairing a semiconductor memory

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Quick Facts
Patent No.
US 6,892,318
App. No.
10/375,994
Granted
May 10, 2005
Kind
B2
Abstract

A block repair device is used in a Dynamic Random Access Memory (DRAM) having a primary array with a defective cell and a redundant array with a redundant row. The block repair device stores a block repair configuration that determines the dimensions (e.g., the number of rows and columns spanned) of a repair block. Routing circuitry is configured by the stored block repair configuration to output some row and column address bits from received row and column addresses in a selected ratio. Comparison circuitry compares the row and column address bits output by the routing circuitry with the address of the defective cell that defines the repair block. When a match occurs, the comparison circuitry implements a block repair by activating the redundant row and by causing data to be written to or read from the activated redundant row instead of the primary array.

Claims (26)

1. A method for substituting a redundant memory cell in a semiconductor memory, comprising:

detecting a defective memory cell in a primary array;

selecting a repair block encompassing the defective memory cell in the primary array;

non-volatilely storing dimensions of the repair block within the semiconductor memory for comparison with a received address during a memory read operation; and

non-volatilely storing a block repair configuration including a redundant row that corresponds to the stored dimensions of the repair block within the semiconductor memory.

2. The method of claim 1 wherein both storing acts comprise storing using non-volatile elements selected from a group comprising fuses, anti-fuses, and flash EEPROM cells.

3. The method of claim 1 further comprising routing received row and column address bits comprises muxing received row and column address bits in accordance with the block repair configuration.

4. The method of claim 1 , further comprising, when a match occurs, disabling memory operations within the primary array by disabling a column decoder associated with the primary array.

5. The method of claim 1 , further comprising writing data to or reading data from a cell within the redundant row comprises writing data to or reading data from a cell selected by a column decoder associated with the redundant row.

6. The method of claim 1 wherein storing a block repair configuration includes programming a non-volatile element to enable block repair with respect to the redundant row.

7. The method of claim 1 wherein storing a block repair configuration includes programming a non-volatile element to disable block repair with respect to the redundant row and thereby enable conventional row repair using the redundant row.

8. The method of claim 7 , further comprising storing row and column address bits of a defective cell that define the stored dimensions of the repair block, said storing comprising storing only row address bits of the defective cell.

9. A method for repairing a semiconductor memory, comprising:

selecting a repair block within a primary array that encompasses a defective cell;

storing row and column address bits of the defective cell that define the repair block;

storing a block repair configuration that corresponds to the repair block;

routing received row and column address bits for determining when a received address falls within the repair block;

disabling the defective cell within the primary array when a match occurs; and

firing a cell within a redundant row selected in accordance with the stored row and column address bits of the defective cell.

10. The method of claim 9 , wherein the storing acts comprise storing in non-volatile elements selected from a group comprising fuses, anti-fuses, and flash EEPROM cells.

11. The method of claim 9 , wherein routing received row and column address bits comprises muxing received row and column address bits in accordance with the block repair configuration.

12. The method of claim 9 , further comprising, when a match occurs, disabling memory operations within the primary array by disabling a column decoder associated with the primary array.

13. The method of claim 9 , wherein firing a cell within the redundant row comprises writing data to or reading data from the cell selected by a column decoder associated with the redundant array.

14. The method of claim 9 , wherein storing a block repair configuration includes programming a non-volatile element to enable block repair with respect to the redundant row.

15. The method of claim 9 , wherein storing a block repair configuration includes programming a non-volatile element to disable block repair with respect to the redundant row and thereby enable conventional row repair using the redundant row.

16. The method of claim 15 , wherein storing row and column address bits of the defective cell that define the repair block comprises storing only row address bits of the defective cell.

Assignments (9)
RELEASE OF SECURITY INTEREST Recorded Nov 10, 2020
From: CPPIB CREDIT INVESTMENTS INC.
To: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
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RELEASE OF U.S. PATENT AGREEMENT (FOR NON-U.S. GRANTORS) Recorded Oct 12, 2018
From: ROYAL BANK OF CANADA, AS LENDER
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AMENDED AND RESTATED U.S. PATENT SECURITY AGREEMENT (FOR NON-U.S. GRANTORS) Recorded Aug 22, 2018
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To: CPPIB CREDIT INVESTMENTS, INC.
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U.S. PATENT SECURITY AGREEMENT (FOR NON-U.S. GRANTORS) Recorded Sep 9, 2014
From: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
To: CPPIB CREDIT INVESTMENTS INC., AS LENDER; ROYAL BANK OF CANADA, AS LENDER
Reel/Frame 033706/0367 →
CHANGE OF ADDRESS Recorded Sep 3, 2014
From: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
To: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
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To: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.; CONVERSANT IP N.B. 868 INC.; CONVERSANT IP N.B. 276 INC.
Reel/Frame 033484/0344 →
CHANGE OF NAME Recorded Mar 13, 2014
From: MOSAID TECHNOLOGIES INCORPORATED
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U.S. INTELLECTUAL PROPERTY SECURITY AGREEMENT (FOR NON-U.S. GRANTORS) - SHORT FORM Recorded Jan 10, 2012
From: 658276 N.B. LTD.; 658868 N.B. INC.; MOSAID TECHNOLOGIES INCORPORATED
To: ROYAL BANK OF CANADA
Reel/Frame 027512/0196 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 10, 2009
From: MICRON TECHNOLOGY INC.
To: MOSAID TECHNOLOGIES INCORPORATED
Reel/Frame 023627/0576 →