Delay locked loop circuit and method
View Patent ↗A delay locked loop includes initialization circuitry that ensures that a DLL is initialized to an operating point that is not to close to either end of a delay vs. control voltage characteristic. The initialization circuitry forces the DLL to initially search for a lock point starting from an initial delay, the delay is varied in one direction, forcing the DLL to skip the first lock point. The initialization circuitry only allows the DLL to vary the delay of the voltage controlled delay loop in the one direction from the initial delay until the operating point is reached.
1. A method for restricting signals outputted by a phase detector during an
initialization process of a Delay Locked Loop (DLL), the outputted signals adapted to be integrated by a control voltage generator to provide a DLL control voltage, the method comprising:
receiving a hold signal to provide an indication, when asserted, that the initialization process is occurring within the DLL; and
if said hold signal is asserted, controlling the outputted signals to cause adjustment of the control voltage in a manner that brings the control voltage closer to a target voltage level situated in a DLL operation region of increased stability.
2. The method as claimed in claim 1 wherein the outputted signals comprise an UP signal and a DOWN signal.
3. The method as claimed in claim 2 wherein the step of controlling includes preventing a selected one of the UP signal and the DOWN signal from being produced.
4. The method as claimed in claim 1 further comprising the step of receiving an indicator that the initialization process has been completed, the step of receiving said indicator occurring after the controlling step.
5. The method as claimed in claim 4 wherein said indicator is said hold signal becoming unasserted.
6. The method as claimed in claim 4 wherein said adjustment of the control voltage is a voltage increasing adjustment and, at a beginning stage of the initialization process, the DLL is operating within an operating region that corresponds to a substantially flat region on a curve of a control voltage versus a controlled delay graph.
7. The method as claimed in claim 4 wherein said adjustment of the control voltage is a voltage decreasing adjustment and, at a beginning stage of the initialization process, the DLL is operating within an operating region that corresponds to a substantially steep region on a curve of a control voltage versus a controlled delay graph.
8. A Delay Locked Loop (DLL) comprising:
a voltage controlled delay line;
a control voltage generator that provides a DLL control voltage to said voltage controlled delay line; and
a phase detector that
i) outputs, under normal operation, at least two signals for integration by said control voltage generator;
ii) receives a hold signal providing an indication, when asserted, that an initialization process is occurring within the DLL; and
iii) if said hold signal is asserted, controls said outputted signals to cause adjustment of said control voltage in a manner that brings said control voltage closer to a target voltage level situated in a DLL operation region of increased stability.
9. The delay locked loop as claimed in claim 8 wherein the outputted signals comprise an UP signal and a DOWN signal.
10. The delay locked loop as claimed in claim 9 wherein said control of the outputted signals includes preventing a selected one of said UP signal and said DOWN signal from being produced.
11. The delay locked loop as claimed in claim 9 wherein said phase detector includes two pairs of UP and DOWN outputs, only one of said pairs of outputs being coupled to inputs of said control voltage generator.
12. The delay locked loop as claimed in claim 11 wherein the one of said pairs of outputs and the other of said pairs of outputs are adapted, respectively, for disablement and enablement during said initialization process.
13. The delay locked loop as claimed in claim 8 wherein upon completion of said initialization process, said phase detector receives a completion indicator.
14. The delay locked loop as claimed in claim 13 wherein said indicator is said hold signal becoming unasserted.
15. The delay locked loop as claimed in claim 13 wherein said adjustment of the control voltage is a voltage increasing adjustment and, at a beginning stage of said initialization process, the DLL is operating within an operating region that corresponds to a substantially flat region on a curve of a control voltage versus a controlled delay graph.
16. The delay locked loop as claimed in claim 13 wherein said adjustment of the control voltage is a voltage decreasing adjustment and, at a beginning stage of said initialization process, the DLL is operating within an operating region that corresponds to a substantially steep region on a curve of a control voltage versus a controlled delay graph.
17. The delay locked loop as claimed in claim 13 further comprising a rough alignment determination component adapted for use during said initialization process.
18. The delay locked loop as claimed in claim 17 wherein said rough alignment determination component is a lock detector, and said phase detector is adapted to provide a fine alignment determination.