Circuit and method for testing multi-device systems
View Patent ↗A method and system for high speed testing of memories in a multi-device system, where individual devices of the multi-device system are arranged in a serial interconnected configuration. High speed testing is achieved by first writing test pattern data to the memory banks of each device of the multi-device system, followed by local test read-out and comparison of the data in each device. Each device generates local result data representing the absence or presence of a failed bit position in the device. Serial test circuitry in each device compares the local result data with global result data from a previous device. The test circuitry compresses this result of this comparison and provides it to the next device as an updated global result data. Hence, the updated global result data will represent the local result data of all the previous devices.
1. A memory device comprising:
memory cells configured to store data;
test circuitry configured to test the memory cells for defects by simultaneously determining mismatching contents between N pairs of memory cells, where N is an integer number, the test circuitry configured to provide N first signals, each indicative of the defective state or the non-defective state of one of the N pairs of memory cells; and
an output circuitry configured to update N second signals received by the memory device based on corresponding N first signals.
2. The memory device of claim 1 , wherein output circuitry updates the second signal only when the second signal corresponds to a non-defective state and the first signal corresponds to a defective state.
3. The memory device of claim 1 , wherein the output circuitry passes through the second signal when the second signal corresponds to a defective state irrespective of the first signal.
4. The memory device of claim 1 , wherein all the memory cells are written to store an identical logic state.
5. The memory device of claim 1 , wherein the output circuitry includes a register for storing the N first signals.
6. The memory device of claim 5 , wherein the register includes a parallel to serial register for receiving the N first signals in parallel, the parallel to serial register being configured to provide each of the N first signals serially in response to a clock signal.
7. The memory device of claim 1 , wherein the test circuitry includes a path selector for selectively providing one of read data and the updated second signal to an output terminal.
8. The memory device of claim 7 , wherein the path selector provides as the read data external read data provided by another memory device, or local read data provided by the memory device.
9. The memory device of claim 8 , wherein the output circuitry includes an input terminal for receiving one of the external read data and the second signal.
10. The memory device of claim 8 , wherein the output circuitry includes a device selector for selectively passing one of the external read data and the local read data.
11. The memory device of claim 1 , wherein the first signal corresponds to a local defect signal and the second signal corresponds to a global defect signal.
12. A memory device comprising:
memory cells configured to store data;
test circuitry including logic circuitry configured to test the memory cells for defects by comparing contents of a first memory cell to a second memory cell, and to provide a first signal indicative of a defective state or a non-defective state, the first signal being provided when the contents of the first memory cell and the second memory cell mismatch; and
an output circuitry configured to update a second signal received by the memory device based on the first signal.
13. The memory device of claim 12 , wherein the logic circuitry includes exclusive OR logic having a first input for receiving the first memory cell content and a second input for receiving the second memory cell content.
14. A memory device comprising:
memory cells configured to store data;
test circuitry configured to test the memory cells for defects and to provide a first signal indicative of a defective state or a non-defective state; and
an output circuitry configured to update a second signal received by the memory device based on the first signal, the output circuitry including a compression circuit for providing the updated second signal in response to the first signal and the second signal, the updated second signal corresponding to a detected defect if at least one of the second signal and the first signal corresponds respectively to a detected defect.
15. The memory device of claim 14 , wherein the test circuitry is configured to determine mismatching contents between pairs of memory cells, thereby indicating that at least one of the pairs of memory cells is defective.
16. The memory device of claim 14 , wherein the compression circuit includes OR logic having a first input for receiving the first signal and a second input for receiving the first signal.
17. The memory device of claim 14 , wherein the compression circuit receives the second signal from the output circuitry, the second signal being provided by another memory device.
18. A memory device comprising:
a first memory bank and a second memory bank having memory cells configured to store data;
the test circuitry configured to test the memory cells for defects by comparing cell data from the first memory bank to cell data of the second memory bank and to provide a first signal indicative of a defective state or a non-defective state; and
an output circuitry configured to update a second signal received by the memory device based on the first signal.