Patent Assignment
Reel/Frame 034979/0850
Release of Security Interest
Recorded: 2015-02-12
Pages: 15
Assignors
CPPIB CREDIT INVESTMENTS INC.
Executed: 2015-02-10
ROYAL BANK OF CANADA
Executed: 2015-02-10
Assignee
CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
390 MARCH ROAD, SUITE 100, OTTAWA, K2K 0G7, CANADA
Covered Properties
(78)
Pulse Counter with Clock Edge Recovery
Packet Based Id Generation for Serially Interconnected Devices
Circuit and Method for Testing Multi-Device Systems
Apparatus and Method for Capturing Serial Input Data
Id Generation Apparatus and Method for Serially Interconnected Devices
Apparatus and Method for Identifying Device Type of Serially Interconnected Devices
Apparatus and Method for Producing Identifiers Regardless of Mixed Device Type in a Serial Interconnection
Apparatus and Method for Producing Device Identifiers for Serially Interconnected Devices of Mixed Type
Reduced Pin Count Interface
Single-Strobe Operation of Memory Devices
Daisy-chain memory configuration and usage
Application:
11/897,105 →
Publication:
US 2009/0063786
Methods and Systems for Failure Isolation and Data Recovery in a Configuration of Series-Connected Semiconductor Devices
Methods and Apparatus for Clock Signal Synchronization in a Configuration of Series-Connected Semiconductor Devices
Ring-Of-Clusters Network Topologies
Apparatus and Method for Identifying Device Types of Series-Connected Devices of Mixed Type
Data Channel Test Apparatus and Method Thereof
Data Flow Control in Multiple Independent Port
Semiconductor Memory Device Suitable for Interconnection in a Ring Topology
Clock Reproducing and Timing Method in a System Having a Plurality of Devices
Mixed Data Rates in Memory Devices and Systems
Mass Data Storage System with Non-Volatile Memory Modules
Serial-Connected Memory System with Output Delay Adjustment
Serial-Connected Memory System with Duty Cycle Correction
Selective Broadcasting of Data in Series Connected Devices
Memory Controller with Flexible Data Alignment to Clock
Device and Method for Transferring Data to a Non-Volatile Memory Device
System Including a Plurality of Encapsulated Semiconductor Chips
Circuit and Method for Testing Multi-Device Systems
Data Mirroring in Serial-Connected Memory System
Error Detection Method and a System Including One or More Memory Devices
Simultaneous Read and Write Data Transfer
Semiconductor Memory with Multiple Wordline Selection
Semiconductor Device with Main Memory Unit and Auxiliary Memory Unit Requiring Preset Operation
Circuit and Method for Testing Multi-Device Systems
Configurable Module and Memory Subsystem
Memory System Having a Plurality of Serially Connected Devices
Data Flow Control in Multiple Independent Port
Apparatus and Method for Capturing Serial Input Data
Apparatus and Method for Producing Identifiers Regardless of Mixed Device Type in a Serial Interconnection
Methods and Systems for Failure Isolation and Data Recovery in a Configuration of Series-Connected Semiconductor Devices
Methods and Apparatus for Clock Signal Synchronization in a Configuration of Series-Connected Semiconductor Devices
Single-Strobe Operation of Memory Devices
High-Speed Interface for Daisy-Chained Devices
Status Indication in a System Having a Plurality of Memory Devices
Application:
13/023,838 →
Publication:
US 2011/0258366
Circuit and Method for Testing Multi-Device Systems
Data Channel Test Apparatus and Method Thereof
System of Interconnected Nonvolatile Memories Having Automatic Status Packet
Method and Apparatus for Concurrently Reading a Plurality of Memory Devices Using a Single Buffer
Application:
13/102,310 →
Publication:
US 2011/0276775
Apparatus and Method for Identifying Device Types of Series-Connected Devices of Mixed Type
Reduced Pin Count Interface
Independent Write and Read Control in Serially-Connected Devices
Data Flow Control in Multiple Independent Port
Power Saving Methods for Use in a System of Serially Connected Semiconductor Devices
Application:
13/425,801 →
Publication:
US 2013/0128678
Connection of Multiple Semiconductor Memory Devices with Chip Enable Function
Application:
13/588,195 →
Publication:
US 2013/0094271
Serially Connected Memory Having Subdivided Data Interface
Flash Memory Module and Memory Subsystem
Apparatus and Method for Producing Device Identifiers for Serially Interconnected Devices of Mixed Type
Package Having Stacked Memory Dies with Serially Connected Buffer Dies
Application:
13/675,163 →
Publication:
US 2013/0119542
Solid State Drive Memory System
Method and Apparatus for Connecting Memory Dies to Form a Memory System
Operational Mode Control in Serial-Connected Memory Based on Identifier
Patent:
44,926 →
Application:
13/774,477 →
Flash Memory Controller Having Dual Mode Pin-Out
Flash Memory Controller Having Multi Mode Pin-Out
Application:
13/836,113 →
Publication:
US 2014/0122777
Single-Strobe Operation of Memory Devices
Memory Controller with Flexible Data Alignment to Clock
Ring Topology Status Indication
Application:
13/903,418 →
Publication:
US 2013/0326090
High Speed Interface for Daisy-Chained Devices
Application:
13/914,126 →
Publication:
US 2013/0275628
System Including a Plurality of Encapsulated Semiconductor Chips
Configurable Module and Memory Subsystem
Simultaneous Read and Write Data Transfer
Memory System Having a Plurality of Serially Connected Devices
Ring-Of-Clusters Network Topologies
Pll Locking Control in Daisy Chained Memory System
Packet Data Id Generation for Serially Interconnected Devices
Application:
14/185,401 →
Publication:
US 2014/0173322
Clock Reproducing and Timing Method in a System Having a Plurality of Devices
Method and Apparatus for Testing Surface Mounted Devices
Memory Controller with Flexible Data Alignment to Clock
Application:
14/486,484 →
Publication:
US 2015/0082072
Error Detection Method and a System Including One or More Memory Device
Application:
14/503,714 →
Publication:
US 2015/0019936
Related Assignments
(10)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
Jul 17, 2008
From: GILLINGHAM, PETER, MR.
To: MOSAID TECHNOLOGIES INCORPORATED
Reel/Frame 021255/0135 →
Change of Address of Assignee
Apr 15, 2009
From: MOSAID TECHNOLOGIES INCORPORATED
To: MOSAID TECHNOLOGIES INCORPORATED
Reel/Frame 022542/0876 →
U.S. Intellectual Property Security Agreement (for Non-U.S. Grantors) - Short Form
Jan 10, 2012
From: 658276 N.B. LTD.; 658868 N.B. INC.; MOSAID TECHNOLOGIES INCORPORATED
To: ROYAL BANK OF CANADA
Reel/Frame 027512/0196 →
Change of Name
Mar 13, 2014
From: MOSAID TECHNOLOGIES INCORPORATED
To: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
Reel/Frame 032439/0638 →
Release of Security Interest
Aug 7, 2014
From: ROYAL BANK OF CANADA
To: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.; CONVERSANT IP N.B. 868 INC.; CONVERSANT IP N.B. 276 INC.
Reel/Frame 033484/0344 →
Change of Address
Sep 3, 2014
From: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
To: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
Reel/Frame 033678/0096 →
U.S. Patent Security Agreement (for Non-U.S. Grantors)
Sep 9, 2014
From: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
To: CPPIB CREDIT INVESTMENTS INC., AS LENDER; ROYAL BANK OF CANADA, AS LENDER
Reel/Frame 033706/0367 →
Assignment of Assignor's Interest
Feb 4, 2015
From: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
To: NOVACHIPS CANADA INC.
Reel/Frame 034888/0904 →
Assignment of Assignor's Interest
Feb 26, 2015
From: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
To: NOVACHIPS CANADA INC.
Reel/Frame 035102/0702 →
Release of U.S. Patent Agreement (for Non-U.S. Grantors)
Oct 12, 2018
From: ROYAL BANK OF CANADA, AS LENDER
To: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
Reel/Frame 047645/0424 →