Data flow control in multiple independent port
View Patent ↗A system includes a memory controller and a plurality of memory devices connected in-series that communicate with the memory controller. Each of the memory devices has multiple independent serial ports for receiving and transmitting data. The memory controller a device address (DA) or ID number for designating a device that executes a command. Data contained in the command sent by the memory controller is captured by an individual link control circuit, in response to internally generated clock with appropriate latencies. The captured data is written into a corresponding memory bank. The data stored in one of a plurality of memory banks of one memory device is read in accordance with the addresses issued by the memory controller. The read data is propagated from the memory device through the series-connected memory devices to the memory controller.
1. A method for use in a memory device, comprising:
receiving an input enable signal having an enable state and a disable state;
while the input enable signal is in the enable state;
receiving an input signal from external to the memory device;
outputting an output signal that is an echo of the input signal;
while the input enable signal is in the disable state;
outputting an output signal that is locally produced by the memory device,
outputting an echo of the input enable signal.
2. The method of claim 1 further comprising:
receiving an output enable signal; and
outputting an echo of the output enable signal.
3. The method of claim 1 further comprising:
receiving a chip select signal having an enable state and disable state; and
while the chip select signal is in the disable state, disabling the outputting of any output signal.
4. The method of claim 2 further comprising:
receiving a chip select signal having an enable state and disable state; and
while the chip select is in the disable state,
disabling the outputting of any output signal, and
disabling the outputting of the echo of at least one of the input enable signal and the output enable signal.
5. A memory device for use in an interconnection configuration including a plurality of memory devices connected in-series, the memory device comprising:
a first input for receiving an input enable signal having an enable state and a disable state;
a second input for receiving an input signal;
a third input for receiving an output enable signal;
a first output for outputting an output signal;
a second output for outputting an echo of the input enable signal;
a third output for outputting an echo of the output enable signal;
a selector for, while the input enable signal is in the enable state, selecting the output signal to be an echo of the input signal, and while the input enable signal is in the disable state, selecting the output signal to be a locally produce signal.
6. The memory device of claim 5 further comprising:
a first buffer for buffering the input signal;
a second buffer for buffering the input enable signal; and
a third buffer for buffering the output enable signal.
7. The memory device of claim 6 further comprising:
a first output provider for providing the echo of the input enable signal from the output of the second buffer; and
a second provider for providing the echo of the output enable signal from the output of the third buffer.
8. The memory device of claim 5 wherein the selector is configured to:
receive the input signal and the locally produced signal, and
receive a control input for causing the selector to output:
the echo of the input signal when the input enable signal is in the enable state, and
the locally produced signal when the input enable signal is in the disable state.
9. The memory device of claim 8 wherein the selector further comprises:
a combiner for logically combining the serial input with the input enable signal to produce a combiner output; and
an internal clock producer for producing a locally clocked version of an output of the combiner as said echo of the input signal.
10. The memory device of claim 8 further comprising:
a chip select input for receiving a chip select signal having an enable state and disable state, while the chip select signal is in the disable state, the memory device disabling the outputting of any output signal and disabling the outputting of the delayed version of the output enable signal.
11. A method for use in a semiconductor device, comprising:
receiving a chip select signal to produce a local chip select signal;
receiving a reset signal to produce a local reset signal;
receiving a clock signal and a complement of the clock signal;
forwarding the clock signal while both the local reset signal is in an enable state and the local chip select signal is in an enable state;
forwarding the complement of the clock signal while both the local reset signal is in the enable state and the local chip select signal is in the enable state; and
producing an internal clock from one of the forwarded clock signal and the forwarded complement of the clock signal.
12. The method of claim 11 wherein the semiconductor device is operable with an SDR (single data rate) clock, the step of producing comprising:
generating an internal clock from one of the forwarded clock signal and the forwarded complement of the clock signal comprises generating a clock pulse in the internal clock for each rising transition of the forwarded clock signal.
13. An apparatus for controlling a semiconductor device, the apparatus comprising:
a first input buffer for receiving and buffering a chip select signal to produce a local chip select signal;
a second input buffer for receiving and buffering a reset signal to produce a local reset signal;
a third input buffer for receiving and buffering a clock signal and forwards the clock signal while both the local reset signal is in an enable state and the local chip select signal is in an enable state;
a fourth input buffer for receiving and buffering a complement of the clock signal while both the local reset signal is in an enable state and the local chip select signal is in an enable state; and
an internal clock producer for producing an internal clock from one of the forwarded clock signal and the forwarded complement of the clock signal.
14. The apparatus of claim 13 wherein the internal clock producer comprises a clock generator for,
when the semiconductor device is operated with an SDR (single data rate), generating a clock pulse in the internal clock for each rising transition of the forwarded dock signal; and
when the semiconductor device is operated with a DDR, generating a clock pulse in the internal clock for each rising transition of the forwarded clock signal and for each rising transition of the forwarded complement of the clock signal.
15. A method comprising:
receiving a chip select signal to produce a local chip select signal;
receiving a reset signal to produce a local reset signal;
receiving a clock signal and a complement of the dock signal;
forwarding the clock signal while both the local reset signal is in an enable state and the local chip select signal is in an enable state;
forwarding the complement of the clock signal while both the local reset signal is in the enable state and the local chip select signal is in the enable state;
in a DDR (double data rate) mode of operation, generating an internal clock from both the clock signal and the complement of the dock signal.
16. The method of claim 15 wherein:
the step of receiving includes buffering a chip select signal to produce a local chip select signal;
the step of receiving includes buffering a reset signal to produce a local reset signal.
17. The method of claim 16 wherein:
In the DDR mode of operation, generating an internal clock from both the forwarded clock signal and the forwarded complement of the clock signal comprises generating a clock pulse in the internal clock for each rising transition of the forwarded clock signal and for each rising transition of the forwarded complement of the clock signal.