Patent Assignment
Reel/Frame 022542/0876
Change of Address of Assignee
Recorded: 2009-04-15
Pages: 9
Assignor
MOSAID TECHNOLOGIES INCORPORATED
Executed: 2009-02-09
Assignee
MOSAID TECHNOLOGIES INCORPORATED
11 HINES ROAD, SUITE 203, OTTAWA, K2K 2X1, CANADA
Covered Properties
(228)
Compare Circuit for a Content Addressable Memory Cell
Daisy Chain Cascading Devices with Input/Output Control
Application:
11/496,278 →
Publication:
US US20070076502A1
Daisy Chain Cascading Devices
Address Assignment and Type Recognition of Serially Interconnected Memory Devices of Mixed Type
System and Method of Operating Memory Devices of Mixed Type
Apparatus and Method for Capturing Serial Input Data
Apparatus and Method for Establishing Device Identifiers for Serially Interconnected Devices
Apparatus and Method for Interfacing to a Memory
Apparatus and Method for Producing Device Identifiers for Serially Interconnected Devices of Mixed Type
Apparatus and Method for Producing Device Identifiers for Serially Interconnected Devices of Mixed Type
Apparatus and Method for Producing Identifiers Regardless of Mixed Device Type in a Serial Interconnection
Apparatus and Method for Identifying Device Types of Series-Connected Devices of Mixed Type
Apparatus and Method for Producing Ids for Interconnected Devices of Mixed Type
Apparatus and Method for Using a Page Buffer of a Memory Device as a Temporary Cache
Asic Design Using Clock and Power Grid Standard Cell
Asynchronous Id Generation
Bias Generator Providing for Low Power, Self-Biased Delay Element and Delay Line
Application:
11/763,506 →
Publication:
US US20080309386A1
Charge Pump for Pll/Dll
Circuit and Method for Glitch Correction
Circuit and Method for Testing Multi-Device Systems
Circuit for Clamping Current in a Charge Pump
Clock Mode Determination in a Memory System
Daisy Chain Cascade Configuration Recognition Technique
Daisy-chain memory configuration and usage
Application:
11/897,105 →
Publication:
US US20090063786A1
Decoding Control with Address Transition Detection in Page Erase Function
Delay Locked Loop Circuit and Method
Dense Mode Coding Scheme
Dynamic Impedance Control for Input/Output Buffers
Dynamic Random Access Memory Device and Method for Self-Refreshing Memory Cells with Temperature Compensated Self-Refresh
Dynamic Random Access Memory Device and Method for Self-Refreshing Memory Cells
Flash Memory Program Inhibit Scheme
Flash Memory System Control Scheme
Flash Multi-Level Threshold Distribution Scheme
Frequency Division Multiplexing System with Selectable Rate
Frequency-Doubling Delay Locked Loop
High Bandwidth Memory Interface
High Bandwidth Memory Interface
Apparatuses for Synchronous Transfer of Information
High Speed Dram Architecture with Uniform Access Latency
Hybrid content addressable memory
Application:
10/809,421 →
Publication:
US US20050213359A1
Hybrid Solid-State Memory System Having Volatile and Non-Volatile Memory
Id Generation Apparatus and Method for Serially Interconnected Devices
Independent Link and Bank Selection
Low Power Memory Architecture
Memory System and Method with Serial and Parallel Modes
Memory System Having Incorrupted Strobe Signals
Storage of Data in Memory via Packet Strobing
Memory with Output Control
Method and Apparatus for Processing Arbitrary Key Bit Length Encryption Operations with Similar Efficiencies
Method and Apparatus for Reducing Pool Starvation in a Shared Memory Switch
Method and Apparatus for Synchronization of Row and Column Access Operations
Method of Configuring Non-Volatile Memory for a Hybrid Disk Drive
Application:
11/428,050 →
Publication:
US US20080005462A1
Methods and Apparatus for Clock Signal Synchronization in a Configuration of Series-Connected Semiconductor Devices
Multi-Level Cell Access Buffer with Dual Function
Modular Command Structure for Memory and Memory System
Multiple Independent Serial Link Memory
Flash Memory Device with Data Output Control
Non-Volatile Memory Serial Core Architecture
Nonvolatile memory system
Application:
11/639,375 →
Publication:
US US20070165457A1
Non-Volatile Memory with Dynamic Multi-Mode Operation
Non-Volatile Semiconductor Memory Having Multiple External Power Supplies
Non-Volatile Semiconductor Memory with Page Erase
Source Side Asymmetrical Precharge Programming Scheme
Packet Based Id Generation for Serially Interconnected Devices
Partial Block Erase Architecture for Flash Memory
Phase Shifting in Dll/Pll
Phase-Locked Loop Circuitry Using Charge Pumps with Current Mirror Circuitry
Power Up Circuit with Low Power Sleep Mode Operation
Pulse Counter with Clock Edge Recovery
Reduced Pin Count Interface
Scalable Memory System
Semiconductor Device and Method for Reducing Power Consumption in a System Having Interconnected Devices
Application:
12/018,272 →
Publication:
US US20080201588A1
Semiconductor Device and Method for Selection and De-Selection of Memory Devices Interconnected in Series
Semiconductor Integrated Circuit Having Current Leakage Reduction Scheme
Semiconductor Memory Asynchronous Pipeline
Data Flow Control in Multiple Independent Port
Simplified Bias Circuitry for Differential Buffer Stage with Symmetric Loads
System Having One or More Memory Devices
Timing Vernier Using a Delay Locked Loop
Trunking in a Matrix
Voltage Down Converter for High Speed Memory
Voltage Level Shifter and Buffer Using Same
Embedded Memory Databus Architecture
Wide Frequency Range Delay Locked Loop
Address Counter Cell
Patent:
5,991,226 →
Application:
08/995,991 →
Addressing for Large Dynamic Ram
Patent:
5,027,329 →
Application:
07/445,448 →
Apparatus and Method for Self-Refreshing Dynamic Random Access Memory Cells
Apparatus and Method for Self-Refreshing Dynamic Random Access Memory Cells
Asynchronous SRAM compatible memory device using DRAM cell and method for driving the same
Bandgap Voltage Generator
Patent:
5,144,223 →
Application:
07/667,880 →
Binary-Ternary Content Addressable Memory
Patent:
6,362,992 →
Application:
09/684,589 →
Bist Memory Test System
Patent:
6,182,257 →
Application:
09/000,968 →
Bitline Precharge
Block Programmable Priority Encoder in a Cam
Block Programmable Priority Encoder in a Cam
Carrier Detection for a Wireless Local Area Network
Patent:
5,131,006 →
Application:
07/633,568 →
Cascading Content Addressable Memory Devices with Programmable Input / Output Connections
Column Redundancy for Content Addressable Memory
Column Redundancy in Semiconductor Memories
Patent:
5,959,903 →
Application:
08/904,153 →
Column Redundancy in Semiconductor Memories
Patent:
6,141,268 →
Application:
09/348,314 →
Content Addressable Memory Architecture
Content Addressable Memory Cell Having Improved Layout
Content Addressable Memory Cell
Content Addressable Memory Cell Having Improved Layout
Delay Locked Loop Implementation in a Synchronous Dynamic Random Access Memory
Patent:
5,796,673 →
Application:
08/319,042 →
Delayed Locked Loop Implementation in a Synchronous Dynamic Random Access Memory
Patent:
6,205,083 →
Application:
09/392,088 →
Delayed Locked Loop Implementation in a Synchronous Dynamic Random Access Memory
Dense Mode Coding Scheme
Dram Page Copy Method
Patent:
5,625,601 →
Application:
08/226,033 →
Dual Match-Line, Twin-Cell, Binary-Ternary Cam
Dynamic content addressable memory cell
Patent:
6,320,777 →
Application:
09/533,128 →
Dynamic Content Addressable Memory Cell
Dynamic Linking of Banks in Configurable Content Addressable Memory Systems
Dynamic Random Access Memory Device and Method for Self-Refreshing Memory Cells with Temperature Compensated Self-Refresh
Dynamic Random Access Memory Device and Method for Self-Refreshing Memory Cells
Dynamic Random Access Memory with Fully Independent Partial Array Refresh Function
Efficient Digital Itu-Compliant Zero-Buffering Dtmf Detection Using the Non-Uniform Discrete Fourier Transform
Patent:
6,370,244 →
Application:
09/054,872 →
Efficient Digital Itu-Compliant Zero-Buffering Dtmf Detection Using the Non-Uniform Discrete Fourier Transform
Error Correction Scheme for Memory
Error Screening Based on Code and Control Information Consistency in a Communication System
Patent:
6,662,339 →
Application:
09/464,042 →
Fast Aging Scheme for Search Engine Databases Using a Linear Feedback Shift Register
Flexible Dram Array
Patent:
5,724,286 →
Application:
08/355,957 →
Flexible Dram Array
Patent:
5,712,823 →
Application:
08/597,510 →
Frequency-Doubling Delay Locked Loop
Patent:
6,441,659 →
Application:
09/562,024 →
Frequency-Doubling Delay Locked Loop
High Bandwidth Memory Interface
High Bandwidth Memory Interface
High Bandwidth Memory Interface
High Output Impedance Charge Pump for Pll/Dll
High Speed Dram Architecture with Uniform Access Latency
High Speed Dram Architecture with Uniform Access Latency
High Speed Dram Architecture with Uniform Access Latency
High Voltage Boosted Word Line Supply Charge Pump Regulator for Dram
Patent:
5,267,201 →
Application:
07/680,994 →
High Voltage Boosted Word Line Supply Charge Pump and Regulator for Dram
Patent:
5,406,523 →
Application:
08/134,621 →
High Voltage Boosted Word Line Supply Charge Pump and Regulator for Dram
Patent:
5,699,313 →
Application:
08/684,252 →
High Voltage Boosted Word Line Supply Charge Pump and Regulator for Dram
Patent:
5,828,620 →
Application:
08/921,579 →
High Voltage Boosted Word Lines Supply Charge Pump and Regulator for Dram
Patent:
6,055,201 →
Application:
09/178,977 →
High voltage boosted word line supply charge pump and regulator for dram
Patent:
6,236,581 →
Application:
09/483,626 →
Boosted Voltage Supply
Boosted Voltage Supply
Boosted Voltage Supply
Large Database Search Using Content Addressable Memory and Hash
Search Engine for Large Database Search Using Hash Pointers
Search Engine for Large Database Search Using Cam and Hash
Link Aggregation
Patent:
6,765,866 →
Application:
09/516,001 →
Low Leakage and Data Retention Circuitry
Low Leakage and Data Retention Circuitry
Low Leakage and Data Retention Circuitry
Low Power Content Addressable Memory Architecture
Patent:
6,584,003 →
Application:
10/134,753 →
Matchline Sensing for Content Addressable Memories
Matchline Sense Circuit and Method
Matchline Sense Circuit and Method
Method and Apparatus for Adaptive Data Compression
Method and Apparatus for an Interleaved Non-Blocking Packet Buffer
Patent:
6,711,170 →
Application:
09/386,589 →
Method and Apparatus for Generating Forward Overrides in a Packet Switch
Patent:
6,661,791 →
Application:
09/473,074 →
Method and Apparatus for Initializing a Delay Locked Loop
Method and Apparatus for Interconnecting Content Addressable Memory Devices
Method and Apparatus for Interconnecting Content Addressable Memory Devices
Method and Apparatus for Performing Repeated Content Addressable Memory Searches
Method and Apparatus for Processing Arbitrary Key Bit Length Encryption Operations with Similar Efficiencies
Method and Apparatus for Providing a Packet Buffer Random Access Memory
Patent:
6,590,901 →
Application:
09/283,778 →
Method and Apparatus for Providing Input Back Pressure in an Output Buffered Switch
Patent:
6,856,595 →
Application:
09/574,621 →
Method and Apparatus for Reducing Latency in a Memory System
Method and Apparatus for Accelerating Retrieval of Data from a Memory System with Cache by Reducing Latency
Method and Apparatus for Accelerating Retrieval of Data from a Memory System with Cache by Reducing Latency
Method and Apparatus for Reducing Pool Starvation in a Shared Memory Switch
Patent:
7,007,071 →
Application:
09/624,276 →
Method and Apparatus for Reordering Entries in a Multi Probe Lookup
Method and Apparatus for Replacing Defective Rows in a Semiconductor Memory Array
Method and Apparatus for Searching a Filtering Database with One Search Operation
Patent:
6,633,567 →
Application:
09/652,196 →
Method and Apparatus for Selectively Disabling Logic in a Semiconductor Device
Patent:
6,434,077 →
Application:
09/804,988 →
Method and Apparatus for Switchably Selecting an Integrated Circuit Operating Mode
Patent:
6,466,048 →
Application:
09/862,339 →
Method and Apparatus for Synchronization of Row and Column Access Operations
Method and Apparatus for Synchronization of Row and Column Access Operations
Method and Apparatus for Synchronization of Row and Column Access Operations
Method and Apparatus for Wire Speed Ip Multicast Forwarding
Patent:
6,754,211 →
Application:
09/453,344 →
Method and Apparatus for Simultaneous Differential Data Sensing and Capture in a High Speed Memory
Method and Circuit for Accelerating Redundant Address Matching
Method and Structure for Reducing Noise Effects in Content Addressable Memories
Patent:
6,563,727 →
Application:
10/208,011 →
Method and System for Packet Encryption
Method for allocating processor resources and system for encrypting data
Dynamic Random Access Memory Using Imperfect Isolating Transistors
Patent:
40,552 →
Application:
10/032,431 →
Method of Multilevel Dram Sense and Restore
Patent:
5,532,955 →
Application:
08/366,921 →
Method of Multilevel Dram Sense and Restore
Patent:
5,612,912 →
Application:
08/584,887 →
Method for Multilevel Dram Sensing
Patent:
6,373,765 →
Application:
09/585,790 →
Multilevel Dram Sensing Analog-to-Digital Converter
Method of Accessing a Communication Medium
Patent:
5,329,531 →
Application:
08/078,099 →
Mismatch-Dependent Power Allocation Technique for Match-Line Sensing in Content-Addressable Memories
Multirate Wireless Data Communication System
Patent:
5,706,428 →
Application:
08/615,408 →
Multi-stage lookup for translating between signals of different bit lengths
Patent:
6,384,750 →
Application:
09/533,724 →
Orthogonal Frequency Division Multiplexing System with Dynamically Scalable Operating Parameters and Method Thereof
Patent:
6,175,550 →
Application:
08/834,684 →
Orthogonal Frequency Division Multiplexing System with Selectable Rate
Patent:
6,563,786 →
Application:
09/224,695 →
Frequency Division Multiplexing System with Selectable Rate
Paralleled Content Addressable Memory Search Engine
Phase Detector Circuit and Method Therefor
Port Packet Queuing
Patent:
7,236,489 →
Application:
09/559,190 →
Portable Hand-Held Reading Device
Patent:
6,037,954 →
Application:
08/899,158 →
Priority Encoder Circuit and Method for Content Addressable Memory
Programmable Interconnect for Semiconductor Devices
Patent:
6,559,544 →
Application:
10/107,821 →
Radio Lan Station with Improved Frame Delimiter Detection in a Spread Spectrum Environment
Patent:
5,151,920 →
Application:
07/757,392 →
Ram Variable Size Block Write
Patent:
5,546,350 →
Application:
08/226,035 →
Regulated Dram Cell Plate and Precharge Voltage Generator
Patent:
6,057,676 →
Application:
09/099,464 →
Searchline Control Circuit and Power Reduction Method
Searchline Control Circuit and Power Reduction Method
Semiconductor Integrated Circuit Having Current Leakage Reduction Scheme
Semiconductor Integrated Circuit Having Low Power Consumption with Self-Refresh
Semiconductor Memory Asynchronous Pipeline
Semiconductor Memory Asynchronous Pipeline
Semiconductor Memory Asynchronous Pipeline
Single Chip Frame Buffer and Graphics Accelerator
Patent:
5,694,143 →
Application:
08/253,271 →
Single Sideband Double Quadrature Modulator
Patent:
5,861,781 →
Application:
08/931,370 →
Sorting Method and Apparatus Using a Cam
Sram-Compatible Memory Device Employing Dram Cells
Staggered Pipeline Access Scheme for Synchronous Random Access Memory
Patent:
5,808,959 →
Application:
08/612,044 →
Staggered Pipeline Access Scheme for Synchronous Random Access MEM0RY
Patent:
5,872,742 →
Application:
09/063,529 →
Start Up Circuit for Delay Locked Loop
Synchronization Circuit and Method with Transparent Latches
Synchronous Sram-Compatible Memory and Method of Driving the Same
Systems and Methods for Minimizing Static Leakage of an Integrated Circuit
Ternary Cam Cell for Reduced Matchline Capacitance
Compare Circuit for a Content Addressable Memory Cell
Timing Vernier Using a Delay Locked Loop
Timing Vernier Using a Delay Locked Loop
Timing Vernier Using a Delay Locked Loop
Timing Vernier Using a Delay Locked Loop
Trunking in a Matrix
Voltage Down Converter for High Speed Memory
Voltage Level Shifter Circuit
Wide Frequency Range Delay Locked Loop
Related Assignments
(14)
Other recorded transfers of the patents in this record — the chain of ownership.
U.S. Intellectual Property Security Agreement (for Non-U.S. Grantors) - Short Form
Jan 10, 2012
From: 658276 N.B. LTD.; 658868 N.B. INC.; MOSAID TECHNOLOGIES INCORPORATED
To: ROYAL BANK OF CANADA
Reel/Frame 027512/0196 →
Change of Name
Mar 13, 2014
From: MOSAID TECHNOLOGIES INCORPORATED
To: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
Reel/Frame 032439/0638 →
Release of Security Interest
Aug 7, 2014
From: ROYAL BANK OF CANADA
To: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.; CONVERSANT IP N.B. 868 INC.; CONVERSANT IP N.B. 276 INC.
Reel/Frame 033484/0344 →
Change of Address
Sep 3, 2014
From: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
To: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
Reel/Frame 033678/0096 →
U.S. Patent Security Agreement (for Non-U.S. Grantors)
Sep 9, 2014
From: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
To: CPPIB CREDIT INVESTMENTS INC., AS LENDER; ROYAL BANK OF CANADA, AS LENDER
Reel/Frame 033706/0367 →
Amended and Restated U.S. Patent Security Agreement (for Non-U.S. Grantors)
Aug 22, 2018
From: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
To: CPPIB CREDIT INVESTMENTS, INC.
Reel/Frame 046900/0136 →
Release of U.S. Patent Agreement (for Non-U.S. Grantors)
Oct 12, 2018
From: ROYAL BANK OF CANADA, AS LENDER
To: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
Reel/Frame 047645/0424 →
Release of Security Interest
Oct 30, 2020
From: CPPIB CREDIT INVESTMENTS INC.
To: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
Reel/Frame 054263/0253 →
Release of Security Interest
Nov 2, 2020
From: CPPIB CREDIT INVESTMENTS INC.
To: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
Reel/Frame 054279/0001 →
Release of Security Interest
Nov 3, 2020
From: CPPIB CREDIT INVESTMENTS INC.
To: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
Reel/Frame 054310/0421 →
Release of Security Interest
Nov 6, 2020
From: CPPIB CREDIT INVESTMENTS INC.
To: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
Reel/Frame 054444/0018 →
Change of Name
Jun 16, 2021
From: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
To: MOSAID TECHNOLOGIES INC.
Reel/Frame 056602/0990 →
Change of Name
Jun 16, 2021
From: CONVERSANT INTELLECTUAL PROPERTY INC.
To: MOSAID TECHNOLOGIES INCORPORATED
Reel/Frame 056602/0253 →
Corrective Assignment to Correct the Conveying Party's Name Previously Recorded at Reel: 056602 Frame: 0253. Assignor(S) Hereby Confirms the Change of Name.
Aug 30, 2023
From: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
To: MOSAID TECHNOLOGIES INCORPORATED
Reel/Frame 064783/0267 →