Granted Patent B2

US 7,593,259 · App. 11/762,330 · Granted Sep 22, 2009

Abstract

Claims (35)

1. A Flash memory device comprising:

a memory array having memory cells arranged in rows and columns, each memory cell erasable to have an erase threshold voltage in an erase voltage domain and programmable to have a program threshold voltage in the erase voltage domain and a program voltage domain;

each memory cell programmable to store two bits of data corresponding to first, second, third, and fourth threshold voltages with the first threshold voltage and the second threshold voltage in the erase voltage domain, and the third threshold voltage and the fourth threshold voltage in the program voltage domain; and,

row control logic for selectively driving a wordline connected to a gate terminal of a memory cell with one of a positive voltage and a negative voltage during program verify and read operations.

2. The Flash memory device of claim 1 , further including a positive voltage generator for providing a positive voltage, and a negative voltage generator for providing a negative voltage.

3. The Flash memory device of claim 1 , wherein the erase voltage domain includes threshold voltages that are negative and the program voltage domain includes threshold voltages that are positive.

4. The Flash memory device of claim 1 , wherein the first threshold voltage corresponds to the erase threshold voltage.

5. A method for programming a Flash memory cell initially erased to have a first threshold voltage in an erase voltage domain, the method comprising:

changing the first threshold voltage of the Flash memory cell to a second threshold voltage, the second threshold voltage being in the erase voltage domain;

precharging a bitline connected to the Flash memory cell to a first voltage level,

driving a wordline connected to the Flash memory cell with a reference voltage in the erase voltage domain, and

sensing a voltage level change in the bitline; and

verifying the second threshold voltage and repeating the step of changing if the Flash memory cell does not have the second threshold voltage.

6. The method of claim 5 , wherein the step of changing includes:

biasing a bitline connected to the Flash memory cell to a programming voltage level; and

driving a wordline connected to the Flash memory cell with a predetermined number of pulses, each pulse having a predetermined step size.

7. The method of claim 5 , wherein the reference voltage is greater than the first threshold voltage and less than the second threshold voltage.

8. The method of claim 6 , wherein the Flash memory cell and a plurality of Flash memory cells form a NAND string, and the step of driving further includes driving wordlines connected to the plurality of Flash memory cells with a pass voltage.

9. A method for reading a Flash memory cell programmable to have an erase voltage domain threshold voltage or a programming domain threshold voltage, the method comprising:

determining one of an erase threshold voltage and the erase voltage domain threshold voltage by applying an erase voltage domain reference voltage to a gate terminal of the Flash memory cell and sensing a bitline voltage connected to the Flash memory cell;

storing a logical state of the Flash memory cell in response to the step of determining one of an erase threshold voltage and the erase voltage domain threshold voltage;

determining one of the erase voltage domain threshold voltage and the programming domain threshold voltage by applying another reference voltage to the gate terminal and sensing the bitline voltage connected to the Flash memory cell; and

updating the logical state in response to the step of determining one of the erase voltage domain threshold voltage and the programming domain threshold voltage.

10. A Flash memory device comprising:

a memory array having memory cells, each memory cell erasable to have a threshold voltage in an erase voltage domain, and programmable to have at least one threshold voltage level in the erase voltage domain and at least another threshold voltage in a program voltage domain; and

each memory cell programmable to store a plurality of bits of data corresponding to first, second, third and fourth threshold voltages with the first threshold voltage and the second threshold voltage in the erase voltage domain, and the third threshold voltage and the fourth threshold voltage in the program voltage domain.

11. The Flash memory device of claim 10 , wherein the erase voltage domain includes threshold voltages that are negative and the program voltage domain includes threshold voltages that are positive.

12. The Flash memory device of claim 10 , wherein the erase voltage domain includes threshold voltages that are positive and the program voltage domain includes threshold voltages that are negative.

13. The Flash memory device of claim 10 , further including row control logic for selectively driving a wordline with a negative voltage and positive voltage in response to a row address.

14. The Flash memory device of claim 13 , further including a first voltage generator for providing the positive voltage and a second voltage generator for providing the negative voltage.

15. The Flash memory device of claim 14 , wherein the row control logic further comprises:

a row decoder for receiving the positive voltage and the negative voltage, the row decoder providing row signals in response to the row address, and

a wordline driver for passing the row signals in response to an enable signal.

16. The Flash memory device of claim 15 , wherein the row control logic further comprises:

a block decoder for providing the enable signal in response to a block address, the enable signal having one of the positive voltage and the negative voltage.

Assignments (13)