Semiconductor device and method for selection and de-selection of memory devices interconnected in series
View Patent ↗A system includes a plurality of memory devices connected in-series that communicate with a memory controller. When a memory device receives a command strobe signal indicating the start of a command having an ID number, the memory device is placed in a de-selected state and the ID number is compared to the memory device's device address. Delayed versions of the command strobe signal and the command are forwarded while the memory device is in the de-selected state. If the ID number matches the device address with reference to the ID number, the memory device is placed in a selected state. In the selected state, the memory device may refrain from forwarding the delayed versions of the command strobe signal and the command, such that if there is a match, a truncated part of the command is forwarded before the memory device is placed in the selected state.
1. A memory device for use in an arrangement of memory devices interconnected in series, the memory device comprising:
a first input for receiving a command input signal containing a command having an identification number;
a second input for receiving a first strobe signal indicating the start of the command;
a third input for receiving clock input;
a fourth input for receiving a second strobe signal, and
logic circuitry configured to:
de-select the memory device in response to the first strobe signal to place the memory device in a de-selected state;
determine whether the identification number of the command matches a device address associated with the memory device;
in response to a determination result, place the memory device in a selected state,
forward the command input signal and the first strobe signal with a delay related to clock cycle latency while the memory device is in the de-selected state;
refrain from for warding the command input signal and the first strobe signal while the memory device is in the selected state; and
forward the second strobe signal with a delay related to a latency that is substantially equal to the latency of a delayed version of the first strobe signal, the second strobe signal containing data enabling data output from the memory device in the selected state.
2. The memory device of claim 1 wherein the logic circuitry is further configured to:
refrain from forwarding the command input signal and the first strobe signal while the memory device is in the selected state; and
transfer the command input signal and the first strobe signal while the memory device is in the de-selected state.
3. The memory device of claim 2 further comprising a third input for receiving clock input, wherein the command input signal is forwarded with a delay related to clock cycle latency while the memory device is in the de-selected state.
4. The memory device of claim 1 further comprising:
a first delay element for providing a delay relating to a clock latency to produce the delayed version of the command input signal;
a second delay element for providing a delay relating to a clock cycle latency to produce the delayed version of the first strobe signal; and
a third delay element for providing a delay relating to a clock cycle latency to produce the delayed version of the second strobe signal.
5. The memory device of claim 1 wherein the logic circuitry comprises:
a comparator for comparing the identification number of the command with the device address associated with the memory device to produce the determination result, and
a pulse producer for producing a pulse responsive to a command strobe on the second input.
6. The memory device of claim 5 wherein the comparator is configured to:
place the memory device in the selected state by asserting an ID match signal and place the memory device in the de-selected state by de-asserting the ID match signal.
7. The memory device of claim 6 wherein each of the device address associated with the memory device and the identification number of the command comprises N-bit binary codes, N being an integer greater than one, the comparator comprises:
exclusive OR circuitry for comparing the device address associated with the memory device to the identification number of the command on a bit-wise basis to produce an N-bit match code signal; and
combinatorial logic circuitry for combining the N-bit match code signal to produce the ID match signal, such that the ID match signal is asserted if each bit of the N-bit match code signal indicates a match, and de-asserted if at least one bit of the N-bit match code signal does not indicate a match.
8. The memory device of claim 7 wherein the comparator further comprises:
a latch for latching the pulse from the pulse generator, wherein the combinatorial logic circuitry combines the N-bit match code signal with an output of the latch, such that the ID match signal is de-asserted in response to the pulse being latched.
9. The memory device of claim 8 wherein the combinatorial logic circuitry comprises:
an alternating cascade of NOR and NAND gates for combining the N signals of the N-bit match code signal and the output of the latch to produce the ID match signal.
10. The memory device of claim 9 wherein N is equal to 8 and the alternating cascade of NOR and NAND gates comprises:
four NOR gates respectively connected to two of the 8 signals of the N-bit match code signal;
two NAND gates having inputs respectively connected to outputs of two NOR gates of the four NOR gates, wherein one NAND gate of the two NAND gates has an input connected to the output of the latch; and
a fifth NOR gate having two inputs connected to an output of each of the two NAND gates, wherein the ID match signal is based on an output of the fifth NOR gate.
11. The memory device of claim 8 further comprising:
control logic and memory having an internal clock generator, the internal clock generator including a command clock generator for generating a command clock while the memory device is in the selected state.
12. The memory device of claim 11 wherein the latch comprises two cross-coupled NAND gates.
13. The memory device of claim 12 wherein the two cross-coupled NAND gates comprise a two-input NAND gate and a three-input NAND gate, wherein:
an inverted version of the command clock is an input of the two-input NAND gate of the latch; and
an inverted version of the pulse from the pulse generator is an input of the three-input NAND gate of the latch.
14. The memory device of claim 8 wherein the memory device operates synchronously with clocks.
15. The memory device of claim 1 wherein the command input signal comprises any one of: a serial link and a parallel link.
16. A method in a memory device in an arrangement of memory devices interconnected in series, the method comprising:
receiving a command input signal containing a command having an identification number;
receiving a first strobe signal indicating the start of the command;
de-selecting the memory device when the first strobe signal is received to place the memory device in a de-selected state;
determining whether the identification number of the command matches a device address associated with the memory device;
placing the memory device in a selected state if the identification number of the command matches the device address associated with the memory device,
forwarding a delayed version of the first strobe signal with a delay relating to a clock cycle latency while the memory device is in the de-selected state;
receiving a second strobe signal containing data strobes enabling data output from the memory device in the selected state; and
forwarding a delayed version of the second strobe signal with a latency that is substantially equal to the latency of the delayed version of the first strobe signal.
17. The method of claim 16 further comprising:
refraining from forwarding the command input signal and the first strobe signal with delays while the memory device is in the selected state.
18. The method of claim 17 wherein the step of forwarding comprises:
forwarding a delayed version of the command input signal with approximately a 1 clock cycle latency while the memory device is in the de-selected state.
19. The method of claim 17 wherein the de-selecting the memory device comprises:
generating a pulse responsive to the first strobe signal; and
placing the memory device in the de-selected state responsive to the pulse.
20. The method of claim 16 wherein the de-selecting the memory device comprises de-asserting an ID match signal and the placing the memory device comprises asserting the ID match signal.