Voltage down converter for high speed memory
View Patent ↗A voltage down converter (VDC) applicable to high-speed memory devices. The VDC includes a steady driver and active driver along with at least one additional transistor. The steady driver and active driver are coupled by a transistor switch during device start-up to provide fast ramp-up to operating voltage and current. After start-up, the steady driver and active drive function to maintain a steady operating voltage and current. An additional transistor is digitally controlled to drive up operating voltage and current upon issuance of an active command representing read, write, and/or refresh of memory. In this manner, the additional transistor provides fast compensation for fluctuations in operating voltage and current brought on by activity in the memory array.
1. A method of providing a supply voltage and current to a Dynamic Random Access Memory (DRAM), said method comprising:
providing a first current to said memory with a first driver circuit including a first comparator and a first driver transistor;
providing a second current to said memory with a second driver circuit including a second comparator and an second driver transistor, the second driver transistor having a small transistor width relative to the first driver transistor; and
providing additional current to said memory by activating at least one additional transistor in response to an active command received from a logic circuit, said active command indicating occurrence of an activity.
2. The method as claimed in claim 1 wherein said activity is selected from the group consisting of reading from memory, writing to memory, and refreshing memory.
3. The method as claimed in claim 1 further including a step of providing further additional current to said memory by way of a further additional transistor in response to another active command received from a logic circuit, said active command indicating occurrence of another activity.
4. The method as claimed in claim 3 wherein said activity is selected from the group consisting of reading from memory and writing to memory.
5. The method as claimed in claim 4 wherein said additional activity is refreshing memory.
6. A method of providing a supply voltage and current to a high-speed memory device having a voltage down converter, said method comprising:
providing a steady state current to said memory device by way of a first driver circuit including a first comparator and a steady driver transistor having a large transistor width;
providing a fluctuating current to said memory device by way of a second driver circuit including a second comparator an active driver transistor having a small transistor width relative to said steady driver; and
providing additional current to said memory device by way of at least one additional transistor in response to an active command received from a logic circuit, said active command indicating occurrence of an activity.
7. A method of providing a supply voltage and current to a Dynamic Random Access Memory device (DRAM), said method comprising:
providing a first current to said memory device with a first driver circuit including a first comparator and a first driver transistor;
providing a second current to said memory device with a second driver circuit including a second comparator and an second driver transistor, the second driver transistor having a small transistor width relative to the first driver transistor; and
providing additional current to said memory device by activating at least one additional transistor in response to an active command received from a logic circuit, said active command indicating occurrence of an activity.