Method and apparatus for accelerating retrieval of data from a memory system with cache by reducing latency
View Patent ↗A memory controller controls a buffer which stores the most recently used addresses and associated data, but the data stored in the buffer is only a portion of a row of data (termed row head data) stored in main memory. In a memory access initiated by the CPU, both the buffer and main memory are accessed simultaneously. If the buffer contains the address requested, the buffer immediately begins to provide the associated row head data in a burst to the cache memory. Meanwhile, the same row address is activated in the main memory bank corresponding to the requested address found in the buffer. After the buffer provides the row head data, the remainder of the burst of requested data is provided by the main memory to the CPU.
1. A method of retrieving data from a memory system having a first memory and a second memory, said method comprising:
(a) receiving a read request with a read address corresponding to a location in the first memory;
(b) searching an address portion of all entries of said second memory for said read address, each entry having a data portion corresponding to each address portion
(c) retrieving the data portion of one entry of the second memory while substantially simultaneously retrieving a remaining portion of said data from said location of the first memory when said read address is found in the address portion of the one entry of the second memory; and
(d) retrieving data from the location of said first memory only when said read address is not found in the address portion of the entries of said second memory.
2. The method of claim 1 , wherein the data portion is a fraction of said data.
3. The method of claim 1 , further including the following step:
(e) storing a duplicate fraction of said data and a duplicate of said read address in the data portion and the address portion respectively if said read address is not found in the address portion of the entries in said second memory.
4. The method of claim 3 , wherein the step of storing includes replacing the data portion and the address portion of an existing entry in the second memory.
5. The method of claim 4 , wherein each entry of said second memory further includes an additional bit for marking the entry as being most recently accessed.
6. The method of claim 5 , further including the step of setting the additional bit corresponding to the stored data portion and address portion, and resetting the additional bits corresponding to the remaining entries of the second memory.
7. The method of claim 1 , wherein each entry of said second memory further includes an additional bit for marking the entry as being most recently accessed.
8. The method of claim 7 , further including the following step:
setting the additional bit in the entry corresponding to the data portion retrieved from the second memory, while resetting the additional bits in the remaining entries of the second memory.