High speed DRAM architecture with uniform access latency
View Patent ↗A Dynamic Random Access Memory (DRAM) performs read, write, and refresh operations. The DRAM includes a plurality of sub-arrays, each having a plurality of memory cells, each of which is coupled with a complementary bit line pair and a word line. The DRAM further includes a word line enable device for asserting a selected one of the word lines and a column select device for asserting a selected one of the bit line pairs. A timing circuit is provided for controlling the word line enable device, the column select device, and the read, write, and refresh operations in response to a word line timing pulse. The read, write, and refresh operation are performed in the same amount of time.
1. A random access memory comprising:
a plurality of memory storage elements arranged in rows and columns and each memory element coupled to a bit line and a word line,
an address register for receiving an address on a first clock edge,
a precharge circuit for precharging the bit line, the precharge circuit responsive to the first clock edge,
a row decoder for:
decoding a first segment of the address; and
activating a word line corresponding to the first segment of the address,
a delay circuit for timing deactivation of the precharge circuit and the activation of the word line,
a column decoder for:
decoding a second segment of the address; and
selecting a bit line corresponding to the second segment of the address,
a sense amplifier for:
sensing data on the bit line; and
restoring data in the memory element coupled to the selected bit line and the activated word line, and
an output circuit for outputting the data.
2. The random access memory as claimed in claim 1 wherein a number of memory elements per bit line is substantially less than in a conventional random access memory adapted for a same process technology.
3. The random access memory as claimed in claim 1 wherein the number of memory elements per bit line is about one quarter of that in the conventional random access memory.
4. The random access memory as claimed in claim 1 wherein the output circuit is an output circuit for outputting the data in response to a second clock edge.
5. The random access memory as claimed in claim 4 wherein a latency time from the first clock edge to the second clock edge is substantially the same for executing reading, writing, and refreshing data commands.
6. The random access memory as claimed in claim 1 wherein the random access memory is a dynamic random access memory.
7. The random access memory as claimed in claim 1 wherein the random access memory is an embedded dynamic random access memory.