Content addressable memory cell having improved layout
View Patent ↗A CAM cell comprises a pair of SRAM cells, each of which comprise a pair of cross coupled inverters for storing a data value and a pair of access devices for accessing a complementary pair of bit lines. The CAM cell ether comprises a pair of compare circuits, each for comparing said data value stored in one of said SRAM cells with a search data value provided on a corresponding search line. The CAM cell has an equivalent number of n-channel and p-channel devices. The CAM cell uses p-channel transistors as access transistors to the SRAM cells in order to improve the efficiency of the layout of the cell array. The implementation ensures a balanced number of p-channel and n-channel devices per cell while still providing excellent functional characteristics.
1. A content addressable memory (CAM) cell comprising:
a cross-coupled inverter pair formed from a first pair of adjacent insulated gate transistors of a first conductivity type coupled to a second pair of adjacent insulated gate transistors of a second conductivity type;
a pair of complementary bitlines coupled to said cross-coupled inverter pair by a third pair of adjacent insulated gate transistors of said first conductivity type;
a comparison circuit formed from a fourth pair of adjacent insulated gate transistors of said second conductivity type and coupled to said cross-coupled inverter pair and a search line for comparing data stored in said cross-coupled inverter pair to a search data value provided on said search line;
wherein said first pair of adjacent insulated gate transistors is positioned adjacent to said second pair and said first and second pairs are positioned adjacent to said third and four pairs, respectively, to form an 4×2 or 2×4 transistor matrix.
2. The CAM cell of claim 1 wherein said first and third pairs of adjacent insulated gate transistors of said first conductivity type are formed in a first well region.
3. The CAM cell of claim 2 wherein said second and fourth pairs of adjacent insulated gate transistors of said second conductivity type are formed in a second well region.
4. The CAM cell of claim 1 wherein said first and second conductivity types are N-channel transistors and P-channel transistors, respectively.
5. The CAM cell of claim 1 wherein said first and second conductivity types are P-channel transistors and N-channel transistors, respectively.
6. The CAM cell of claim 3 wherein said first and second well regions are separated by one spacing region.
7. The CAM cell of claim 1 wherein said CAM cell is coupled to a second CAM cell to form a ternary CAM cell.