Phase shifting in DLL/PLL
View Patent ↗The disclosure relates to phase shifting in Delay Locked Loops (DLLs) and Phase-Locked Loops (PLLs). A charge pump in the DLL or PLL includes a capacitor connected in parallel to an output node. A primary current switching circuit charges the capacitor with a source current and discharges the capacitor with a sink current. A supplemental source circuit sources a positive phase shift producing current which has a range of magnitudes. A magnitude of the positive phase shift producing current is determined by at least one source selection signal. A supplemental sink circuit for sources a negative phase shift producing current which has a range of magnitudes. A magnitude of the negative phase shift producing current is determined by at least one sink selection signal.
1. A charge pump circuit comprising:
a capacitor connected in parallel to an output node;
a reference current source generating a reference current;
a primary current switching circuit for charging said capacitor with a source current and for discharging said capacitor with a sink current, said source current tracking the reference current and said sink current tracking the reference current;
a supplemental source circuit including an offset generator for sourcing, in response to a bias voltage, a positive phase shift producing current having a range of magnitudes, the supplemental source circuit also including a programmable array of transistors for providing the bias voltage, the bias voltage being adjustable in response to at least one source selection signal, said positive phase shift producing current tracking the same current tracked by said source current; and
a supplemental sink circuit for sourcing a negative phase shift producing current having a range of magnitudes, a magnitude of the negative phase shift producing current being determined by at least one sink selection signal, said negative phase shift producing current tracking the same current tracked by said sink current.
2. The charge pump circuit of claim 1 , wherein the supplemental source circuit includes pairs of select transistors and sourcing transistors connected in series, each of the pairs adjusting the magnitude of the positive phase shift producing current in response to the at least one source selection signal.
3. The charge pump circuit of claim 1 , wherein the supplemental sink circuit includes pairs of select transistors and sinking transistors connected in series, each of the pairs adjusting the magnitude of the negative phase shift producing current in response to the at least one sink selection signal.
4. The charge pump circuit of claim 1 , wherein the programmable array of transistors includes pairs of select transistors and sourcing transistors connected in series, each of the pairs adjusting the bias voltage in response to the at least one source selection signal.
5. The charge pump circuit of claim 4 , wherein the offset generator includes a current source transistor having a gate for receiving the bias voltage.
6. The charge pump circuit of claim 5 , wherein the offset generator includes an enable transistor for coupling a voltage supply to the current source transistor in response to an enable signal.
7. The charge pump circuit of claim 5 , wherein each of the sourcing transistors are diode connected and in a current mirror configuration with the current source transistor.
8. The charge pump circuit of claim 5 , wherein the supplemental source circuit includes a bias transistor connected between the gate of the current source transistor and a voltage supply, the bias transistor sinking current that tracks the reference current.
9. The charge pump circuit of claim 1 , wherein the offset generator is a first offset generator, the programmable array is a first programmable array, the bias voltage is a first bias voltage, and the supplemental sink circuit includes
a second offset generator for sinking the negative phase shift producing current in response to a second bias voltage,
second programmable array of transistors for providing the second bias voltage, the second bias voltage being adjustable in response to the at least one sink selection signal.
10. The charge pump circuit of claim 9 , wherein the second programmable array of transistors includes pairs of select transistors and sinking transistors connected in series, each of the pairs adjusting the second bias voltage in response to the at least one sink selection signal.
11. The charge pump circuit of claim 10 , wherein the second offset generator includes a current sink transistor having a gate for receiving the second bias voltage.
12. The charge pump circuit of claim 11 , wherein the second offset generator includes an enable transistor for coupling a voltage supply to the current sink transistor in response to an enable signal.
13. The charge pump circuit of claim 11 , wherein each of the sinking transistors are diode connected and in a current mirror configuration with the current sink transistor.
14. The charge pump circuit of claim 11 , wherein the supplemental sink circuit includes a bias transistor connected between the gate of the current sink transistor and a voltage supply, the bias transistor sourcing current that tracks the reference current.
15. A charge pump circuit comprising:
a capacitor connected in parallel to an output node;
a reference current source generating a reference current;
a primary current switching circuit for charging said capacitor with a source current and for discharging said capacitor with a sink current, said source current tracking the reference current and said sink current tracking the reference current;
a supplemental source circuit for sourcing a positive phase shift producing current having a range of magnitudes, a magnitude of the positive phase shift producing current being determined by at least one source selection signal, said positive phase shift producing current tracking the same current tracked by said source current; and
a supplemental sink circuit having an offset generator for sourcing a negative phase shift producing current having a range of magnitudes in response to a bias voltage, and a programmable array of transistors for providing the bias voltage, said negative phase shift producing current tracking the same current tracked by said sink current.
16. The charge pump circuit of claim 15 , wherein the offset generator is a first offset generator, the programmable array is a first programmable array, the bias voltage is a first bias voltage, and the supplemental source circuit includes
a second offset generator for sourcing the positive phase shift producing current in response to a second bias voltage,
second programmable array of transistors for providing the second bias voltage, the second bias voltage being adjustable in response to the at least one source selection signal.
17. The charge pump circuit of claim 16 , wherein the second programmable array of transistors includes pairs of select transistors and sourcing transistors connected in series, each of the pairs adjusting the second bias voltage in response to the at least one source selection signal.
18. The charge pump circuit of claim 17 , wherein the second offset generator includes a current source transistor having a gate for receiving the second bias voltage.