Apparatus and method for self-refreshing dynamic random access memory cells
View Patent ↗A dynamic random access memory (DRAM) having DRAM cells coupled to wordlines and bitlines. In a self-refresh mode, the cells coupled with the even numbered rows retain main data previously stored therein and the assistant data, which is logically opposite to the main data, is overwritten into the cells coupled with the wordlines of the odd numbered rows. When the DRAM enters the self-refresh mode, a starting refresh address for the self-refresh mode is detected. If the detected starting refresh address does not match with a predetermined correct address set for the self-refresh operation mode, a dummy refresh cycle will be established in an entry-burst self-refresh period. During the dummy refresh cycle, a dummy refresh command is added to increment an internal row address counter that provides row addresses for self-refreshing the cells of the selected wordlines within the cell array.
1. A dynamic random access memory (DRAM) device comprising:
an array of DRAM cells arranged in rows by columns, each DRAM cell of the array being coupled to a wordline of a corresponding row and a bitline of a corresponding column; and
refresh circuitry for refreshing data stored in the DRAM cells coupled to wordlines of a first set of rows as main data and for overwriting assistant data into the DRAM cells coupled to wordlines of a second set of rows in a self-refresh mode, the assistant data being opposite data to the main data, each row of the second set being adjacent to each row of the first set, the refresh circuitry comprising:
a mode entry detector for detecting an entry into the self-refresh mode to retain the main data and to overwrite the assistant data, the mode entry detector producing a first self-refresh mode signal when entry into the self-refresh mode is detected;
dummy establishing circuitry for detecting a starting refresh address for operation of the self-refresh mode in response to the first self-refresh mode signal, and for executing a dummy refresh cycle if the detected starting refresh address mismatches with a predetermined address, wherein no refresh operation occurs during the dummy refresh cycle;
entry signal producing circuitry for producing a self-refresh entry signal in response to the first self-refresh mode signal; and
adoption circuitry for adopting the dummy refresh cycle in the self-refresh mode.
2. The DRAM device of claim 1 , wherein:
the adoption circuitry comprises burst circuitry for determining a first burst refresh cycle in response to the self-refresh entry signal; and
the dummy establishing circuitry comprises dummy circuitry for determining the dummy refresh cycle in response to the first self-refresh mode signal and a row address signal.
3. The DRAM device of claim 2 , wherein:
the adoption circuitry further comprises entry burst establishing circuitry for combining the dummy refresh cycle with the first burst refresh cycle to establish an entry-burst refresh period; and
the burst circuitry comprises
a refresh burst generator for generating a first burst clock pulse signal during the first burst refresh cycle; and
burst period decision circuitry for counting the burst clock pulses up to a predetermined value that corresponds to the number of the wordlines to produce a second self-refresh mode signal, the second self-refresh mode signal causing the self-refresh entry signal to be disabled and the first burst refresh cycle to be ceased.
4. The DRAM device of claim 3 , wherein:
the refresh circuitry further comprises oscillation circuitry for establishing a self-refresh cycle in response to the second self-refresh mode signal; and
the adoption circuitry further comprises combining circuitry for combining the self-refresh cycle with the entry-burst refresh period.
5. The DRAM device of claim 2 , wherein the dummy circuitry comprises:
a pulse generator for generating a dummy pulse signal having a predetermined pulse width driven by the first self-refresh mode signal.
6. The DRAM device of claim 4 , wherein the refresh circuitry further comprises:
a mode exit detector for detecting an exit from the self-refresh mode to disable the first self-refresh mode signal; and
exit signal producing circuitry for producing a self-refresh exit signal in response to the first self-refresh mode signal being disabled.
7. The DRAM device of claim 6 , wherein:
the burst circuitry further initiates a second burst refresh cycle in response to the self-refresh exit signal; and
the combining circuitry further combines the second burst refresh cycle with the self-refresh cycle with the entry-burst refresh period.
8. The DRAM device of claim 7 , wherein the refresh burst generator further generates a second burst clock signal during the second burst refresh cycle.
9. The DRAM device of claim 8 , wherein the adoption circuitry further comprises:
signal combining circuitry for combining the dummy pulse signal, the first burst clock pulse signal, the oscillation pulse signal and the second burst clock signal to produce the refresh clock pulse signal for self-refreshing the cells.
10. The DRAM device of claim 9 , wherein:
the refresh burst generator comprises a pulse generator for generating pulses as the second burst clock pulse signal in response to the exit from the self-refresh mode; and
the burst period decision circuitry comprises a pulse counter for counting the pulses of the burst clock pulse signal up to a predetermined value that corresponds to the number of the wordlines of the DRAM device, thereby producing the second self-refresh mode signal upon count of the predetermined value.
11. The DRAM device of claim 10 , wherein the oscillation circuitry further comprises:
oscillation control circuitry for controlling the generation of the oscillation pulse signal by the self-refresh oscillator in response to the first and second self-refresh mode signal.
12. The DRAM device of claim 11 , wherein:
the entry signal producing circuitry comprises first latch circuitry for holding the self-refresh entry signal when the generation of the first self-refresh mode signal and a given logic state of the row address signal overlap; and
the exit signal producing circuitry comprises second latch circuitry for holding the self-refresh exit signal when the ceasing of the first self-refresh mode signal and the given logic state of the row address signal overlap.
13. The DRAM device of claim 12 , wherein the dummy circuitry comprises:
third latch circuitry for disabling the generation of the dummy pulse signal when the row address signal mismatches the predetermined address.
14. The DRAM device of claim 1 , wherein the dummy establishing circuitry comprises:
a detector for detecting the starting refresh address based on one bit of the refresh row address represented by the refresh signal.
15. The DRAM device of claim 14 , wherein the detector for detecting the starting refresh address comprises:
a one-bit detector for detecting a first address bit of the refresh signal for addressing a first row of the array.